| RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints C Georgakidis, I Lilitsis, G Stanimeropoulos, C Sotiriou 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021 | 3 | 2021 |
| Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows N Blias, I Lilitsis, S Simoglou, E Bakas, C Sotiriou 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration …, 2022 | 1 | 2022 |
| Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model S Simoglou, I Lilitsis, N Blias, C Sotiriou 2024 25th International Symposium on Quality Electronic Design (ISQED), 1-8, 2024 | | 2024 |
| Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis C Georgakidis, D Valiantzas, S Simoglou, I Lilitsis, N Chatzivangelis, ... 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2023 | | 2023 |
| Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops N Chatzivangelis, D Valiantzas, C Sotiriou, I Lilitsis 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration …, 2022 | | 2022 |
| Single Event Transients Generation and Propagation Flow using Commercial EDA Tools S Simoglou, C Georgakidis, I Lilitsis, C Sotiriou, M Andjelkovic, M Krstic 2021 IEEE 32nd International Conference on Microelectronics (MIEL), 333-336, 2021 | | 2021 |
| 36rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems AA Koufopoulou, A Papadimitriou, A Pikrakis, M Psarakis, D Hely, ... | | |
Stavros SimoglouSynopsys Inc.Verified email at uth.gr
