| Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019 | 64 | 2019 |
| Adapting interconnect technology to multigate transistors for optimum performance D Prasad, A Ceyhan, C Pan, A Naeemi IEEE Transactions on Electron Devices 62 (12), 3938-3944, 2015 | 22 | 2015 |
| A 64-bit arm CPU at cryogenic temperatures: Design technology co-optimization for power and performance R Saligram, D Prasad, D Pietromonaco, A Raychowdhury, B Cline 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 15 | 2021 |
| Impact of interconnect variability on circuit performance in advanced technology nodes D Prasad, C Pan, A Naeemi 2016 17th International Symposium on Quality Electronic Design (ISQED), 398-404, 2016 | 15 | 2016 |
| A high-density logic-on-logic 3DIC design using face-to-face hybrid wafer-bonding on 12nm FinFET process S Sinha, S Hung, D Fisher, X Xu, C Chao, P Chandupatla, F Frederick, ... 2020 IEEE International Electron Devices Meeting (IEDM), 15.1. 1-15.1. 4, 2020 | 13 | 2020 |
| Modeling interconnect variability at advanced technology nodes and potential solutions D Prasad, C Pan, A Naeemi IEEE Transactions on Electron Devices 64 (3), 1246-1253, 2017 | 10 | 2017 |
| A holistic evaluation of buried power rails and back-side power for sub-5 nm technology nodes SST Nibhanupudi, D Prasad, S Das, O Zografos, A Robinson, A Gupta, ... IEEE Transactions on Electron Devices 69 (8), 4453-4459, 2022 | 9 | 2022 |
| Interconnect design and technology optimization for conventional and emerging nanoscale devices: A physical design perspective D Prasad, A Naeemi 2018 IEEE International Electron Devices Meeting (IEDM), 5.1. 1-5.1. 4, 2018 | 9 | 2018 |
| Cryo-computing for infrastructure applications: A technology-to-microarchitecture co-optimization study D Prasad, M Vangala, M Bhargava, A Beckers, A Grill, D Tierno, ... 2022 International Electron Devices Meeting (IEDM), 23.5. 1-23.5. 4, 2022 | 8 | 2022 |
| Power from Below: Buried Interconnects Will Help Save Moore's Law B Cline, D Prasad, E Beyne, O Zografos IEEE Spectrum 58 (9), 46-51, 2021 | 7 | 2021 |
| Crafting power aware coverage: verification closure with UPF IEEE 1801 P Khondkar, P Yeung, D Prasad, G Chidolue, M Bhargava Journal of VLSI Design and Verification, 6-17, 2017 | 6 | 2017 |
| Interconnect design for evolutionary, and revolutionary transistor technologies D Prasad, A Naeemi 2017 IEEE International Interconnect Technology Conference (IITC), 1-3, 2017 | 4 | 2017 |
| Systems, Devices, and Methods for Dedicated Low Temperature Design and Operation DMS Prasad, DV Pietromonaco, BT Cline US Patent App. 17/798,518, 2023 | 1 | 2023 |
| Wirelength distribution schemes and techniques DMS Prasad, SP Sinha, BT Cline, SL Moore US Patent 10,657,218, 2020 | 1 | 2020 |
| Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule D Prasad, S Sinha, B Cline, S Moore, A Naeemi Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 1 | 2018 |
| A novel performance model for state-of-the-art processors by modernization of Rent's rule D Prasad, S Sinha, B Cline, S Moore, A Naeemi 2017 IEEE International Electron Devices Meeting (IEDM), 20.6. 1-20.6. 4, 2017 | 1 | 2017 |
| Systems, Devices, and Methods of Charge-Based Storage Elements DMS Prasad, DV Pietromonaco, BT Cline, M Bhargave US Patent App. 17/902,798, 2024 | | 2024 |
| Systems, Devices, and Methods of Cache Memory DMS Prasad, K Nathella, DV Pietromonaco US Patent App. 17/866,448, 2024 | | 2024 |
| Wirelength distribution schemes and techniques DMS Prasad, SP Sinha, BT Cline, SL Moore US Patent 11,126,778, 2021 | | 2021 |
| Ensuring reliable computation with unreliable devices in the era of AI/ML D Prasad, R Aitken Design-Process-Technology Co-optimization XV 11614, 1161404, 2021 | | 2021 |
Brian ClineFounder, entrepreneur: Stealth-mode startupVerified email at lumoniq.com
