Siddharth Garg
Siddharth Garg
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Badnets: Identifying vulnerabilities in the machine learning model supply chain
T Gu, B Dolan-Gavitt, S Garg
arXiv preprint arXiv:1708.06733, 2017
Fine-pruning: Defending against backdooring attacks on deep neural networks
K Liu, B Dolan-Gavitt, S Garg
International Symposium on Research in Attacks, Intrusions, and Defenses …, 2018
Badnets: Evaluating backdooring attacks on deep neural networks
T Gu, K Liu, B Dolan-Gavitt, S Garg
IEEE Access 7, 47230-47244, 2019
Securing computer hardware using 3d integrated circuit ({IC}) technology and split manufacturing for obfuscation
F Imeson, A Emtenan, S Garg, M Tripunitara
22nd {USENIX} Security Symposium ({USENIX} Security 13), 495-510, 2013
The EDA challenges in the dark silicon era: Temperature, reliability, and variability perspectives
M Shafique, S Garg, J Henkel, D Marculescu
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes.
M El Massad, S Garg, MV Tripunitara
NDSS, 1-14, 2015
Safetynets: Verifiable execution of deep neural networks on an untrusted cloud
Z Ghodsi, T Gu, S Garg
Advances in Neural Information Processing Systems 30, 2017
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators
J Zhang, K Rangineni, Z Ghodsi, S Garg
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors
B Raghunathan, Y Turakhia, S Garg, D Marculescu
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 39-44, 2013
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator
JJ Zhang, T Gu, K Basu, S Garg
2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018
Reverse engineering camouflaged sequential circuits without scan access
M El Massad, S Garg, M Tripunitara
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 33-40, 2017
Verifiable asics
RS Wahby, M Howald, S Garg, A Shelat, M Walfish
2016 IEEE Symposium on Security and Privacy (SP), 759-778, 2016
HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors
Y Turakhia, B Raghunathan, S Garg, D Marculescu
Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013
Securing hardware accelerators: A new challenge for high-level synthesis
C Pilato, S Garg, K Wu, R Karri, F Regazzoni
IEEE Embedded Systems Letters 10 (3), 77-80, 2017
Dark silicon as a challenge for hardware/software co-design: Invited special session paper
M Shafique, S Garg, T Mitra, S Parameswaran, J Henkel
Proceedings of the 2014 International Conference on Hardware/Software …, 2014
Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling
DC Juan, S Garg, J Park, D Marculescu
2013 International Conference on Hardware/Software Codesign and System …, 2013
Logic locking for secure outsourced chip fabrication: A new attack and provably secure defense mechanism
ME Massad, J Zhang, S Garg, MV Tripunitara
arXiv preprint arXiv:1703.10187, 2017
Exploiting process variability in voltage/frequency control
S Herbert, S Garg, D Marculescu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011
Variability-aware dark silicon management in on-chip many-core systems
M Shafique, D Gnad, S Garg, J Henkel
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 387-392, 2015
TAO: Techniques for algorithm-level obfuscation during high-level synthesis
C Pilato, F Regazzoni, R Karri, S Garg
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
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