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Tao Chen
Tao Chen
Verified email at mediatek.com
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Cited by
Cited by
Year
USER-SMILE: Ultrafast stimulus error removal and segmented model identification of linearity errors for ADC built-in self-test
T Chen, X Jin, RL Geiger, D Chen
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (7), 2059-2069, 2017
422017
A low-cost on-chip built-in self-test solution for ADC linearity test
T Chen, C Park, H Meng, D Zhou, J Silva-Martinez, RL Geiger, D Chen
IEEE Transactions on Instrumentation and Measurement 69 (6), 3516-3526, 2019
262019
Ultrafast stimulus error removal algorithm for ADC linearity test
T Chen, D Chen
2015 IEEE 33rd VLSI Test Symposium (VTS), 1-5, 2015
252015
High-purity sine wave generation using nonlinear DAC with predistortion based on low-cost accurate DAC–ADC co-testing
Y Zhuang, B Magstadt, T Chen, D Chen
IEEE Transactions on Instrumentation and Measurement 67 (2), 279-287, 2017
232017
An on-chip ADC BIST solution and the BIST enabled calibration scheme
X Jin, T Chen, M Jain, AK Barman, D Kramer, D Garrity, R Geiger, D Chen
2017 IEEE International Test Conference (ITC), 1-10, 2017
162017
Low-cost dithering generator for accurate ADC linearity test
Y Duan, T Chen, D Chen
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1474-1477, 2016
152016
Low-cost and accurate DAC linearity test with ultrafast segmented model identification of linearity errors and removal of measurement errors (uSMILE-ROME)
SK Chaganti, T Chen, Y Zhuang, D Chen
2018 IEEE International Instrumentation and Measurement Technology …, 2018
142018
Effect of flicker noise on SEIR for accurate ADC linearity testing
Y Zhuang, T Chen, S Chaganti, D Chen
2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015
122015
A 5nm 3.4 GHz tri-gear ARMv9 CPU subsystem in a fully integrated 5G flagship mobile SoC
A Nayak, HC Chen, H Mair, R Lagerquist, T Chen, A Rajagopalan, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 50-52, 2022
72022
A 12-bit 125-MS/s 2.5-bit/cycle SAR-based pipeline ADC employing a self-biased gain boosting amplifier
C Park, T Chen, K Noh, D Zhou, S Prakash, MN Alizadeh, AI Karsilayan, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3618-3629, 2020
72020
Dynamic comparator
T Chen, X Jin, JP Schat
US Patent 10,505,519, 2019
72019
An ultrafast multibit/stage pipelined ADC testing and calibration method
T Chen, C Park, SK Chaganti, J Silva-Martinez, RL Geiger, D Chen
IEEE Transactions on Instrumentation and Measurement 69 (3), 729-738, 2019
72019
High-constancy offset generator robust to cdac nonlinearity for SEIR-based ADC BIST
Y Duan, T Chen, Z Liu, X Zhang, D Chen
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 3016-3019, 2015
72015
4.1 A 7nm 5G Mobile SoC Featuring a 3.0 GHz Tri-Gear Application Processor Subsystem
H Chen, R Lagerquist, A Nayak, H Mair, G Manoharan, E Wang, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 54-56, 2021
62021
Built-in self-test and self-calibration for analog and mixed signal circuits
T Chen, D Chen
2019 IEEE International Test Conference (ITC), 1-8, 2019
42019
Accurate linearity testing with impure sinusoidal stimulus robust against flicker noise
Y Zhuang, T Chen, S Chaganti, D Chen
2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016
42016
A low-cost dithering method for improving ADC linearity test applied in uSMILE algorithm
Y Duan, T Chen, D Chen
Journal of Electronic Testing 33, 709-720, 2017
32017
Method for testing analog-to-digital converter and system therefor
T Chen, X Jin
US Patent 9,473,164, 2016
32016
Method for testing differential analog-to-digital converter and system therefor
T Chen, DA Garrity, X Jin
US Patent 9,438,262, 2016
32016
Apparatuses involving calibration of input offset voltage and signal delay of circuits and methods thereof
T Chen, X Jin, JP Schat
US Patent 11,585,849, 2023
22023
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Articles 1–20