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Liyang Lai
Liyang Lai
Calypto Design Systems
在 mentor.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
Signature based diagnosis for logic BIST
WT Cheng, M Sharma, T Rinderknecht, L Lai, C Hill
2006 IEEE International Test Conference, 1-9, 2006
712006
Built-in self-test of integrated circuits using selectable weighting of test patterns
L Lai, WT Cheng, TH Rinderknecht
US Patent 7,840,865, 2010
642010
Logic BIST with scan chain segmentation
L Lai, JH Patel, T Rinderknecht, WT Cheng
2004 International Conferce on Test, 57-66, 2004
332004
Hardware efficient LBIST with complementary weights
L Lai, JH Patel, T Rinderknecht, WT Cheng
2005 International Conference on Computer Design, 479-481, 2005
302005
Detection and diagnosis of static scan cell internal defect
R Guo, L Lai, H Yu, WT Cheng
2008 IEEE International Test Conference, 1-10, 2008
262008
Diagnosis and layout aware (DLA) scan chain stitching
J Ye, Y Huang, Y Hu, WT Cheng, R Guo, L Lai, TP Tai, X Li, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (3), 466-479, 2014
252014
Two-dimensional scan architecture
Y Huang, WT Cheng, R Guo, M Sharma, L Lai
US Patent 9,222,978, 2015
152015
Detection and diagnosis of scan cell internal defects
R Guo, L Lai, Y Huang, WT Cheng
US Patent 9,086,459, 2015
132015
X-tolerant compactor with on-chip registration and signature-based diagnosis
J Tyszer, J Rajski, G Mrugalski, N Mukherjee, M Kassab, WT Cheng, ...
IEEE Design & Test of Computers 24 (5), 476-485, 2007
132007
GPU-based hybrid parallel logic simulation for scan patterns
L Lai, Q Zhang, H Tsai, WT Cheng
2020 IEEE International Test Conference in Asia (ITC-Asia), 118-123, 2020
102020
Logic BIST using constrained scan cells
L Lai, T Rinderknecht, WT Cheng, JH Patel
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 199-205, 2004
102004
Programmable scan-based logic built-in self test
L Lai, WT Cheng, T Rinderknecht
16th Asian Test Symposium (ATS 2007), 371-377, 2007
92007
Test access architecture for stacked memory and logic dies
WT Cheng, R Guo, Y Huang, L Lai, E Racine, M Keim, R Press, J Ye, ...
US Patent 9,689,918, 2017
82017
Design for testing 3D TSVs connecting memory die and logic die
J Ye, R Guo, Y Hu, W Zheng, Y Huang, L Lai, X Li
Journal of Computer-Aided Design & Computer Graphics 26 (1), 146-153, 2014
82014
Test architecture for characterizing interconnects in stacked designs
WT Cheng, R Guo, Y Huang, L Lai, J Ye, Y Hu
US Patent 9,335,376, 2016
62016
Diagnosis-aware scan chain stitching
Y Huang, WT Cheng, R Guo, L Lai
US Patent 9,015,543, 2015
52015
Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System
J Hu, G Dai, L Wang, L Lai, Y Huang, H Yang, Y Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022
42022
GPGPU-based ATPG system: Myth or reality?
L Lai, KH Tsai, H Li
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
42018
Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree
Y Huang, WT Cheng, TP Tai, L Lai, R Guo, FM Kuo, YS Chen
International Symposium for Testing and Failure Analysis 38268, 103-111, 2011
42011
Scalable parallel static learning
X Lin, L Lai, H Li
2021 IEEE International Test Conference in Asia (ITC-Asia), 1-6, 2021
22021
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