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Shaolan Li
Shaolan Li
Verified email at ece.gatech.edu - Homepage
Title
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Cited by
Year
A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure
S Li, B Qiao, M Gandara, DZ Pan, N Sun
IEEE Journal of Solid-State Circuits 53 (12), 3484-3496, 2018
602018
A 174.3-dB FoM VCO-Based CT Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS
S Li, A Mukherjee, N Sun
IEEE Journal of Solid-State Circuits 52 (7), 1940-1952, 2017
572017
Wellgan: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout
B Xu, Y Lin, X Tang, S Li, L Shen, N Sun, DZ Pan
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
382019
Geniusroute: A new analog routing paradigm using generative neural network guidance
K Zhu, M Liu, Y Lin, B Xu, S Li, X Tang, N Sun, DZ Pan
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
332019
A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer
J Liu, S Li, W Guo, G Wen, N Sun
IEEE Journal of Solid-State Circuits 54 (2), 428-440, 2018
312018
Magical: Toward fully automated analog ic layout leveraging human and machine intelligence
B Xu, K Zhu, M Liu, Y Lin, S Li, X Tang, N Sun, DZ Pan
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
292019
A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure
S Li, B Qiao, M Gandara, N Sun
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 234-236, 2018
272018
A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier
X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, S Li, ...
IEEE Journal of Solid-State Circuits 55 (12), 3248-3259, 2020
232020
A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology
B Xu, S Li, N Sun, DZ Pan
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
232017
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- M Structure
W Zhao, S Li, B Xu, X Yang, X Tang, L Shen, N Lu, DZ Pan, N Sun
IEEE Journal of Solid-State Circuits 55 (3), 666-679, 2019
212019
18.2 a 16fJ/Conversion-step time-domain two-step Capacitance-to-Digital converter
X Tang, S Li, L Shen, W Zhao, X Yang, R Williams, J Liu, Z Tan, N Hall, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 296-297, 2019
21*2019
Hierarchical and analytical placement techniques for high-performance analog circuits
B Xu, S Li, X Xu, N Sun, DZ Pan
Proceedings of the 2017 ACM on International Symposium on Physical Design, 55-62, 2017
182017
A 0.028mm219.8fJ/step 2nd-order VCO-based CT ΔΣ modulator using an inherent passive integrator and capacitive feedback in 40nm CMOS
S Li, N Sun
2017 Symposium on VLSI Circuits, C36-C37, 2017
172017
A 0.029MM2 17-FJ/Conv.-Step CT ADC with 2nd-Order Noise-Shaping SAR Quantizer
J Liu, S Li, W Guo, G Wen, N Sun
2018 IEEE symposium on VLSI circuits, 201-202, 2018
162018
27.3 A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation
TH Wang, R Wu, V Gupta, S Li
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 374-376, 2021
122021
3.4 A 0.01mm2 25W 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor
L Shen, Y Shen, X Tang, CK Hsu, W Shi, S Li, W Zhao, A Mukherjee, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 64-66, 2019
122019
Device layer-aware analytical placement for analog circuits
B Xu, S Li, CW Pui, D Liu, L Shen, Y Lin, N Sun, DZ Pan
Proceedings of the 2019 International Symposium on Physical Design, 19-26, 2019
112019
A Second-Order Purely VCO-Based CT ADC Using a Modified DPLL Structure in 40-nm CMOS
Y Zhong, S Li, X Tang, L Shen, W Zhao, S Wu, N Sun
IEEE Journal of Solid-State Circuits 55 (2), 356-368, 2019
102019
A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO
A Mukherjee, M Gandara, B Xu, S Li, L Shen, X Tang, D Pan, N Sun
IEEE Solid-State Circuits Letters 2 (1), 1-4, 2019
102019
A two-step ADC with a continuous-time SAR-based first stage
L Shen, Y Shen, Z Li, W Shi, X Tang, S Li, W Zhao, M Zhang, Z Zhu, N Sun
IEEE Journal of Solid-State Circuits 54 (12), 3375-3385, 2019
92019
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