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Rani S. Ghaida
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Year
Mask assignment for multiple patterning lithography
RS Abou Ghaida, KB Agarwal, LW Liebmann, SR Nassif
US Patent 8,434,033, 2013
402013
Resolving double patterning conflicts
RS Abou Ghaida, KB Agarwal
US Patent 8,359,556, 2013
392013
Resolving double patterning conflicts
RS Abou Ghaida, KB Agarwal, IBM Corporation
US Patent 20,130,007,674, 2013
392013
Multiple patterning layout decomposition for ease of conflict removal
RS Abou Ghaida, KB Agarwal, LW Liebmann, SR Nassif
US Patent 8,516,403, 2013
382013
Layout decomposition and legalization for double-patterning technology
RS Ghaida, KB Agarwal, SR Nassif, X Yuan, LW Liebmann, P Gupta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
352013
Single-mask double-patterning lithography for reduced cost and improved overlay control
RS Ghaida, G Torres, P Gupta
IEEE Transactions on Semiconductor Manufacturing 24 (1), 93-103, 2010
342010
Single-mask double-patterning lithography
P Gupta, RS Ghaida
US Patent 8,415,089, 2013
262013
Design-overlay interactions in metal double patterning
RS Ghaida, P Gupta
Design for Manufacturability through Design-Process Integration III 7275 …, 2009
262009
A novel methodology for triple/multiple-patterning layout decomposition
RS Ghaida, KB Agarwal, LW Liebmann, SR Nassif, P Gupta
Design for Manufacturability through Design-Process Integration VI 8327, 176-183, 2012
252012
DRE: A framework for early co-evaluation of design rules, technology choices, and layout methodologies
RS Ghaida, P Gupta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
232012
Electrical modeling of lithographic imperfections
TB Chan, RS Ghaida, P Gupta
2010 23rd International Conference on VLSI Design, 423-428, 2010
232010
A framework for early and systematic evaluation of design rules
RS Ghaida, P Gupta
Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009
222009
A framework for double patterning-enabled design
RS Ghaida, KB Agarwal, SR Nassif, X Yuan, LW Liebmann, P Gupta
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 14-20, 2011
192011
Within-layer overlay impact for design in metal double patterning
RS Ghaida, P Gupta
IEEE Transactions on Semiconductor Manufacturing 23 (3), 381-390, 2010
172010
Framework for exploring the interaction between design rules and overlay control
RS Ghaida, M Gupta, P Gupta
Journal of Micro/Nanolithography, MEMS, and MOEMS 12 (3), 033014-033014, 2013
162013
A framework for exploring the interaction between design rules and overlay control
RS Ghaida, M Gupta, P Gupta
Metrology, Inspection, and Process Control for Microlithography 8681, 86810C, 2013
162013
Random yield prediction based on a stochastic layout sensitivity model
RS Ghaida, K Doniger, P Zarkesh-Ha
IEEE transactions on semiconductor manufacturing 22 (3), 329-337, 2009
152009
Comprehensive die-level assessment of design rules and layouts
RS Ghaida, Y Badr, M Gupta, N Jin, P Gupta
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 61-66, 2014
132014
A methodology for the early exploration of design rules for multiple-patterning technologies
RS Ghaida, T Sahu, P Kulkarni, P Gupta
Proceedings of the International Conference on Computer-Aided Design, 50-56, 2012
132012
Layout pattern correction for integrated circuits
R Abou Ghaida, A Mohyeldin, P Pathak, S Muddu, V Dai, L Capodieci
US Patent 8,898,606, 2014
122014
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