| Spin orbit torque non-volatile flip-flop for high speed and low energy applications K Jabeur, G Di Pendina, F Bernard-Granger, G Prenat IEEE electron device letters 35 (3), 408-410, 2014 | 105 | 2014 |
| Comparison of Verilog‐A compact modelling strategies for spintronic devices K Jabeur, F Bernard‐Granger, G Di Pendina, G Prenat, B Dieny Electronics letters 50 (19), 1353-1355, 2014 | 28 | 2014 |
| SPITT: A magnetic tunnel junction SPICE compact model for STT-MRAM F Bernard-Granger, B Dieny, R Fascio, K Jabeur Proceedings of the MOS-AK Workshop of the Design, Automation & Test in …, 2015 | 23 | 2015 |
| Integration and automation of DoseMapper in a logic Fab APC system: application for 45/40/28nm node B Le Gratiet, C Salagnon, J de Caunes, M Mikolajczak, V Morin, ... Metrology, Inspection, and Process Control for Microlithography XXVI 8324 …, 2012 | 13 | 2012 |
| Magnetic tunnel junction compact device model for electrical simulations of Spintronics components V Javerliac, F Bernard-Granger, L Prejbeanu Magnetism and Magnetic Materials, 2005 | 13 | 2005 |
| Reducing system power consumption using check-pointing on nonvolatile embedded magnetic random access memories C Layer, L Becker, K Jabeur, S Claireux, B Dieny, G Prenat, GD Pendina, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (4), 1-24, 2016 | 6 | 2016 |
| Implementation of a DFM Checker for 65nm and Beyond P Le Maitre, P Simon, R Goncalves, L Le Cam, R Boone, X Hours, ... EDA Tech Forum, 1-9, 2007 | 6 | 2007 |
| Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks C Layer, K Jabeur, S Gros, L Becker, P Paoli, F Bernard-Granger, ... 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015 | 4 | 2015 |
| In-field in-design metrology target integration for advanced cd and overlay process control via dosemapper and high order overlay correction for 28nm and beyond logic node J Ducote, F Bernard-Granger, B Le-Gratiet, R Bouyssou, R Bianchini, ... Metrology, Inspection, and Process Control for Microlithography XXVII 8681 …, 2013 | 4 | 2013 |
| Fully integrated litho aware PnR design solution C Beylier, C Moyroud, FB Granger, F Robert, E Yesilada, Y Trouiller, ... Design for Manufacturability through Design-Process Integration VI 8327, 91-99, 2012 | 4 | 2012 |
| Multi-port non-volatile memory F Bernard-Granger, V Javerliac US Patent 9,653,135, 2017 | 3 | 2017 |
| Hybrid STT/CMOS design of an interrupt based instant on/off mechanism for low-power SOC C Layer, K Jabeur, L Becker, B Dieny, S Gros, V Javerliac, P Paoli, ... 2015 IEEE Computer Society Annual Symposium on VLSI, 315-320, 2015 | 2 | 2015 |
| RET and DFM techniques for sub 30nm E Yesilada, J Entradas, C Gardin, JN Pena, A Villaret, V Farys, C Beylier, ... Optical Microlithography XXV 8326, 839-847, 2012 | 2 | 2012 |
| Multi-port non-volatile memory BGF JAVERLIAC Virgile | | 2015 |
| Modélisation et simulation de micro systèmes magnétiques-Application aux têtes de lecture GMR pour enregistreur sur bande et aux mémoires magnétiques de type MRAM F Bernard-Granger Université Joseph-Fourier-Grenoble I, 2004 | | 2004 |
| Modélisation d’un problème de bulles magnétiques F Bernard-Granger, J Oullier | | |
Gregory DI PENDINAEngineer - Researcher @ CNRS ; CEA-SPINTEC LabVerified email at cea.fr
