| CMOS digital integrated circuits SM Kang, Y Leblebici MacGraw-Hill, 2003 | 2567 | 2003 |
| Neuromorphic computing using non-volatile memory GW Burr, RM Shelby, A Sebastian, S Kim, S Kim, S Sidler, K Virwani, ... Advances in Physics: X 2 (1), 89-124, 2017 | 1253 | 2017 |
| Neuromorphic computing with multi-memristive synapses I Boybat, M Le Gallo, SR Nandakumar, T Moraitis, T Parnell, T Tuma, ... Nature communications 9 (1), 2514, 2018 | 748 | 2018 |
| A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... IEEE Journal of Solid-State Circuits 48 (12), 3049-3058, 2013 | 412 | 2013 |
| Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs M De Marchi, D Sacchetto, S Frache, J Zhang, PE Gaillardon, Y Leblebici, ... 2012 International Electron Devices Meeting, 8.4. 1-8.4. 4, 2012 | 327 | 2012 |
| Dynamic thermal management in 3D multicore architectures AK Coskun, JL Ayala, D Atienza, TS Rosing, Y Leblebici 2009 Design, Automation & Test in Europe Conference & Exhibition, 1410-1415, 2009 | 260 | 2009 |
| MoS2 Transistors Operating at Gigahertz Frequencies D Krasnozhon, D Lembke, C Nyffeler, Y Leblebici, A Kis Nano letters 14 (10), 5905-5911, 2014 | 224 | 2014 |
| 22.1 a 90gs/s 8b 667mw 64× interleaved sar adc in 32nm digital soi cmos L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 222 | 2014 |
| Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor V Majidzadeh, A Schmid, Y Leblebici IEEE Transactions on biomedical circuits and systems 5 (3), 262-271, 2011 | 219 | 2011 |
| Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power) GW Burr, P Narayanan, RM Shelby, S Sidler, I Boybat, C Di Nolfo, ... 2015 IEEE International Electron Devices Meeting (IEDM), 4.4. 1-4.4. 4, 2015 | 199 | 2015 |
| A capacitive threshold-logic gate H Ozdemir, A Kepkep, B Pamir, Y Leblebici, U Cilingiroglu IEEE Journal of Solid-State Circuits 31 (8), 1141-1150, 1996 | 165 | 1996 |
| Omnidirectional sensor array system L Bagnato, L Jacques, P Vandergheynst, H Afshari, A Schmid, Y Leblebici US Patent 9,876,953, 2018 | 152 | 2018 |
| Implementing ultra-high-value floating tunable CMOS resistors A Tajalli, Y Leblebici, EJ Brauer IEE Electronics Letters 44 (5), 349-350, 2008 | 150 | 2008 |
| Subthreshold source-coupled logic circuits for ultra-low-power applications A Tajalli, EJ Brauer, Y Leblebici, E Vittoz IEEE Journal of Solid-State Circuits 43 (7), 1699-1710, 2008 | 144 | 2008 |
| Memristive-biosensors: A new detection method by using nanofabricated memristors S Carrara, D Sacchetto, MA Doucey, C Baj-Rossi, G De Micheli, ... Sensors and Actuators B: Chemical 171, 449-457, 2012 | 135 | 2012 |
| Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs M De Marchi, J Zhang, S Frache, D Sacchetto, PE Gaillardon, Y Leblebici, ... IEEE Electron Device Letters 35 (8), 880-882, 2014 | 126 | 2014 |
| Hot-carrier reliability of MOS VLSI circuits Y Leblebici, SMS Kang Springer Science & Business Media, 2012 | 111 | 2012 |
| Top–down fabrication of gate-all-around vertically stacked silicon nanowire FETs with controllable polarity M De Marchi, D Sacchetto, J Zhang, S Frache, PE Gaillardon, Y Leblebici, ... IEEE transactions on Nanotechnology 13 (6), 1029-1038, 2014 | 110 | 2014 |
| Review of advances in neural networks: Neural design technology stack AD Almási, S Woźniak, V Cristea, Y Leblebici, T Engbersen Neurocomputing 174, 31-41, 2016 | 99 | 2016 |
| CMOS digital integrated circuits: analysis and design Y Leblebici, SM Kang McGraw-Hill, 1996 | 97 | 1996 |
