| AI hardware acceleration with analog memory: micro-architectures for low energy at high speed GWB H.-Y. Chang, P. Narayanan, S. C. Lewis, N. C. .P. Farinha, K. Hosokawa,C ... IBM Journal of Research and Development, 2019 | 52 | 2019 |
| PipeBERT: High-throughput BERT Inference for ARM Big. LITTLE Multi-core Processors HY Chang, SH Mozafari, C Chen, JJ Clark, BH Meyer, WJ Gross Journal of Signal Processing Systems, 1-18, 2022 | 9 | 2022 |
| A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance ER Hsieh, HY Chang, SS Chung, TP Chen, SA Huang, TJ Chen, O Cheng, ... 2019 Symposium on VLSI Technology, T138-T139, 2019 | 7 | 2019 |
| High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline HY Chang, SH Mozafari, JJ Clark, BH Meyer, WJ Gross Proceedings of the Great Lakes Symposium on VLSI 2023, 455-459, 2023 | | 2023 |
| High-throughput BERT Inference for ARM Big. LITTLE Multi-core Processors HY Chang McGill University, 2023 | | 2023 |
Brett H MeyerAssociate Professor of ECE, McGill UniversityVerified email at mcgill.ca
