| A RISC-V instruction set processor-micro-architecture design and analysis A Raveendran, VB Patil, D Selvakumar, V Desalphine 2016 International Conference on VLSI Systems, Architectures, Technology and …, 2016 | 35 | 2016 |
| Out of order floating point coprocessor for RISC V ISA V Patil, A Raveendran, PM Sobha, AD Selvakumar, D Vivian 2015 19th International Symposium on VLSI Design and Test, 1-7, 2015 | 29 | 2015 |
| A novel parametrized fused division and square-root POSIT arithmetic architecture A Raveendran, S Jean, J Mervin, D Vivian, D Selvakumar 2020 33rd International Conference on VLSI Design and 2020 19th …, 2020 | 15 | 2020 |
| P-fma: A novel parameterized posit fused multiply-accumulate arithmetic processor S Jean, A Raveendran, AD Selvakumar, G Kaur, SG Dharani, ... 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 7 | 2021 |
| Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA V Desalphine, S Dashora, L Mali, K Suhas, A Raveendran, D Selvakumar 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-4, 2020 | 5 | 2020 |
| RISC-V out-of-order data conversion co-processor A Raveendran, V Patil, V Desalphine, PM Sobha, AD Selvakumar 2015 19th International Symposium on VLSI Design and Test, 1-2, 2015 | 4 | 2015 |
| Design and analysis of Posit Quire processing engine for neural network applications PJ Edavoor, A Raveendran, D Selvakumar, V Desalphine, G Raut 2023 36th International Conference on VLSI Design and 2023 22nd …, 2023 | 1 | 2023 |
| Risc-v half precision floating point instruction set extensions and co-processor A Raveendran, S Jean, J Mervin, D Vivian, D Selvakumar VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 1 | 2019 |
| Design and Analysis of Posit Processing Engine with Embedded Activation Functions for Neural Network Applications PJ Edavoor, A Raveendran, V Desalphine, D Selvakumar Emerging Electronic Devices, Circuits and Systems: Select Proceedings of …, 2023 | | 2023 |
| PositGen-A Verification Suite for Posit Arithmetic A Kulkarni, S Pattanshetty, A Raveendran, D Selvakumar, S Jean, ... 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | | 2021 |
| Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU A Raveendran, V Kumar, D Vivian, D Selvakumar VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | | 2019 |
| CUSTOM PROCESSOR DESIGN USING VHDL A Raveendran | | |
