| Flow control in networking system-on-chip verification S Krishnamurthy, DK Garg, G Ankit, S Khaitan, S Gupta, JR Stickley, ... US Patent 10,628,548, 2020 | 7 | 2020 |
| Off to the races with your accelerated SystemVerilog testbench H Van der Schoot, A Saha, A Garg, K Suresh Design and Verification Conference and Exhibition (DVCon), 2011 | 6 | 2011 |
| Adapting the dmtcp plugin model for checkpointing of hardware emulation R Garg, K Arya, J Cao, G Cooperman, J Evans, A Garg, NA Rosenberg, ... arXiv preprint arXiv:1703.00897, 2017 | 2 | 2017 |
| Back-pressure in virtual machine interface G Ankit, JR Stickley, DK Garg, GAE Ghattas, HMS Tawfik, AGY Khalil US Patent 10,572,623, 2020 | 1 | 2020 |
| A Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches H van der Schoot, S Anoop, G Ankit, S Krishnamurthy Verification Horizons, 2011 | 1 | 2011 |
| Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation Environment JE Ankit Garg, K. Suresh, Gene Cooperman, Rohan Garg 2018 Design and Verification Conference and Exhibition (DVCON-US'18), 2018 | | 2018 |
