| 14.6 A 0.62 mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector K Bong, S Choi, C Kim, S Kang, Y Kim, HJ Yoo 2017 IEEE International Solid-State Circuits Conference (ISSCC), 248-249, 2017 | 176 | 2017 |
| 4.6 A1. 93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications S Park, K Bong, D Shin, J Lee, S Choi, HJ Yoo 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 107 | 2015 |
| A low-power convolutional neural network face recognition processor and a CIS integrated with always-on face detector K Bong, S Choi, C Kim, D Han, HJ Yoo IEEE Journal of Solid-State Circuits 53 (1), 115-123, 2017 | 104 | 2017 |
| An energy-efficient and scalable deep learning/inference processor with tetra-parallel MIMD architecture for big data applications SW Park, J Park, K Bong, D Shin, J Lee, S Choi, HJ Yoo IEEE transactions on biomedical circuits and systems 9 (6), 838-848, 2015 | 61 | 2015 |
| A 1.93 tops/w scalable deep learning/inference processor with tetra-parallel mimd architecture for big data applications HJ Yoo, S Park, K Bong, D Shin, J Lee, S Choi IEEE international solid-state circuits conference, 80-81, 2015 | 58 | 2015 |
| A 2.1 TFLOPS/W mobile deep RL accelerator with transposable PE array and experience compression C Kim, S Kang, D Shin, S Choi, Y Kim, HJ Yoo 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 136-138, 2019 | 54 | 2019 |
| A 9.02 mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices S Choi, J Lee, K Lee, HJ Yoo 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 220-222, 2018 | 53 | 2018 |
| DT-CNN: Dilated and transposed convolution neural network accelerator for real-time image segmentation on mobile devices D Im, D Han, S Choi, S Kang, HJ Yoo 2019 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2019 | 46 | 2019 |
| 14.1 A 126.1 mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glasses S Park, S Choi, J Lee, M Kim, J Park, HJ Yoo 2016 IEEE International Solid-State Circuits Conference (ISSCC), 254-255, 2016 | 37 | 2016 |
| Low-power convolutional neural network processor for a face-recognition system K Bong, S Choi, C Kim, HJ Yoo IEEE Micro 37 (6), 30-38, 2017 | 34 | 2017 |
| DT-CNN: An energy-efficient dilated and transposed convolutional neural network processor for region of interest based image segmentation D Im, D Han, S Choi, S Kang, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (10), 3471-3483, 2020 | 33 | 2020 |
| An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications C Kim, K Bong, I Hong, K Lee, S Choi, HJ Yoo ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 255-258, 2017 | 27 | 2017 |
| The development of silicon for AI: Different design approaches KJ Lee, J Lee, S Choi, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4719-4732, 2020 | 14 | 2020 |
| A 4.45 ms low-latency 3D point-cloud-based neural network processor for hand pose estimation in immersive wearable devices D Im, S Kang, D Han, S Choi, HJ Yoo 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 12 | 2020 |
| A 0.5 V 9.26 μW 15.28 mΩ/√ Hz Bio-Impedance Sensor IC With 0.55° Overall Phase Error. K Kim, JH Kim, S Gweon, J Lee, M Kim, Y Lee, S Kim, HJ Yoo ISSCC, 364-366, 2019 | 12 | 2019 |
| CNNP-v2: An energy efficient memory-centric convolutional neural network processor architecture S Choi, K Bong, D Han, HJ Yoo 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 11 | 2019 |
| An energy-efficient deep reinforcement learning accelerator with transposable PE array and experience compression C Kim, S Kang, S Choi, D Shin, Y Kim, HJ Yoo IEEE Solid-State Circuits Letters 2 (11), 228-231, 2019 | 7 | 2019 |
| A cmos image sensor-based stereo matching accelerator with focal-plane sparse rectification and analog census transform C Kim, K Bong, S Choi, KJ Lee, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 63 (12), 2180-2188, 2016 | 6 | 2016 |
| A 43.7 mw 94 fps cmos image sensor-based stereo matching accelerator with focal-plane rectification and analog census transformation C Kim, K Bong, S Choi, HJ Yoo 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1418-1421, 2016 | 5 | 2016 |
| CNNP-v2: A memory-centric architecture for low-power CNN processor on domain-specific mobile devices S Choi, K Bong, D Han, HJ Yoo IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (4 …, 2019 | 4 | 2019 |
