| Architecture of cobweb-based redundant TSV for clustered faults T Ni, D Liu, Q Xu, Z Huang, H Liang, A Yan IEEE transactions on very large scale integration (VLSI) systems 28 (7 …, 2020 | 144 | 2020 |
| Non-intrusive online distributed pulse shrinking-based interconnect testing in 2.5 D IC T Ni, H Chang, T Song, Q Xu, Z Huang, H Liang, A Yan, X Wen IEEE transactions on circuits and systems II: express briefs 67 (11), 2657-2661, 2019 | 53 | 2019 |
| A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC T Ni, Q Xu, Z Huang, H Liang, A Yan, X Wen IEEE transactions on computer-aided design of integrated circuits and …, 2020 | 29 | 2020 |
| Clustered fault tolerance TSV planning for 3-D integrated circuits Q Xu, S Chen, X Xu, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 23 | 2017 |
| Fast thermal analysis for fixed-outline 3D floorplanning Q Xu, S Chen Integration 59, 157-167, 2017 | 20 | 2017 |
| Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning Q Xu, S Chen, B Li Applied Soft Computing 40, 150-160, 2016 | 17 | 2016 |
| Temperature-aware floorplanning for fixed-outline 3D ICs T Ni, H Chang, S Zhu, L Lu, X Li, Q Xu, H Liang, Z Huang IEEE Access 7, 139787-139794, 2019 | 15 | 2019 |
| High-speed adder design space exploration via graph neural processes H Geng, Y Ma, Q Xu, J Miao, S Roy, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 14 | 2021 |
| Adaptive 3D-IC TSV fault tolerance structure generation S Chen, Q Xu, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 13 | 2018 |
| Generalized fault-tolerance topology generation for application-specific network-on-chips S Chen, M Ge, Z Li, J Huang, Q Xu, F Wu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 12 | 2019 |
| Fault tolerance in memristive crossbar-based neuromorphic computing systems Q Xu, S Chen, H Geng, B Yuan, B Yu, F Wu, Z Huang Integration 70, 70-79, 2020 | 11 | 2020 |
| Memristive crossbar mapping for neuromorphic computing systems on 3D IC Q Xu, H Geng, S Chen, B Yu, F Wu ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (1 …, 2019 | 11 | 2019 |
| Integrated optimization of partitioning, scheduling, and floorplanning for partially dynamically reconfigurable systems S Chen, J Huang, X Xu, B Ding, Q Xu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 11 | 2018 |
| Reliability-driven neuromorphic computing systems design Q Xu, J Wang, H Geng, S Chen, X Wen 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 8 | 2021 |
| Integer linear programming based fault-tolerant topology synthesis for application-specific NoC Z Li, J Huang, Q Xu, S Chen 2017 IEEE 12th International Conference on ASIC (ASICON), 96-99, 2017 | 7 | 2017 |
| GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning Q Xu, H Geng, S Chen, B Yuan, C Zhuo, Y Kang, X Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 6 | 2021 |
| Anti-interference low-power double-edge triggered flip-flop based on C-elements Z Huang, X Yang, T Song, H Qi, Y Ouyang, T Ni, Q Xu Tsinghua Science and Technology 27 (1), 1-12, 2021 | 6 | 2021 |
| Reliability-driven neural network training for memristive crossbar-based neuromorphic computing systems J Wang, Q Xu, B Yuan, S Chen, B Yu, F Wu 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2020 | 5 | 2020 |
| An integrated optimization framework for partitioning, scheduling and floorplanning on partially dynamically reconfigurable fpgas X Xu, Q Xu, J Huang, S Chen Proceedings of the on Great Lakes Symposium on VLSI 2017, 403-406, 2017 | 5 | 2017 |
| Synthesizing brain-network-inspired interconnections for large-scale network-on-chips M Ge, X Ni, X Qi, S Chen, J Huang, Y Kang, F Wu ACM Transactions on Design Automation of Electronic Systems (TODAES) 27 (1 …, 2021 | 3 | 2021 |
