| 3-D AND-type flash memory architecture with high-κ gate dielectric for high-density synaptic devices YT Seo, D Kwon, Y Noh, S Lee, MK Park, SY Woo, BG Park, JH Lee IEEE Transactions on Electron Devices 68 (8), 3801-3806, 2021 | 19 | 2021 |
| Low-power and high-density neuron device for simultaneous processing of excitatory and inhibitory signals in neuromorphic systems SY Woo, D Kwon, N Choi, WM Kang, YT Seo, MK Park, JH Bae, BG Park, ... IEEE Access 8, 202639-202647, 2020 | 16 | 2020 |
| Field effect transistor-type devices using high-κ gate insulator stacks for neuromorphic applications MK Park, HN Yoo, YT Seo, SY Woo, JH Bae, BG Park, JH Lee ACS Applied Electronic Materials 2 (2), 323-328, 2019 | 13 | 2019 |
| Cointegration of the TFT-type AND flash synaptic array and CMOS circuits for a hardware-based neural network MK Park, WM Kang, RH Koo, JH Kim, J Hwang, JH Bae, JJ Kim, JH Lee IEEE Transactions on Electron Devices 70 (1), 93-98, 2022 | 5 | 2022 |
| Fast-response/recovery In2O3 thin-film transistor-type NO2 gas sensor with floating-gate at low temperature G Yeom, D Kwon, W Shin, MK Park, JJ Kim, JH Lee Sensors and Actuators B: Chemical 394, 134477, 2023 | 4 | 2023 |
| Implementation of synaptic device using various high-k gate dielectric stacks YT Seo, MK Park, JH Bae, BG Park, JH Lee Journal of Nanoscience and Nanotechnology 20 (7), 4292-4297, 2020 | 4 | 2020 |
| CMOS-compatible low-power gated diode synaptic device for Hardware-based neural network MK Park, HN Yoo, J Hwang, SY Woo, D Kwon, YT Seo, JH Lee, JH Bae IEEE Transactions on Electron Devices 69 (2), 832-837, 2021 | 3 | 2021 |
| Direct Gradient Calculation: Simple and Variation‐Tolerant On‐Chip Training Method for Neural Networks H Kim, J Hwang, D Kwon, J Kim, MK Park, J Im, BG Park, JH Lee Advanced Intelligent Systems 3 (8), 2100064, 2021 | 3 | 2021 |
| Hardware-Based Ternary Neural Network Using AND-Type Poly-Si TFT Array and Its Optimization Guideline D Kwon, MK Park, WM Kang, J Hwang, RH Koo, JH Bae, JH Lee IEEE Transactions on Electron Devices, 2023 | 2 | 2023 |
| Effect of layer-specific synaptic retention characteristics on the accuracy of deep neural networks HN Yoo, MK Park, BG Park, JH Lee Solid-State Electronics 200, 108570, 2023 | 2 | 2023 |
| Power and Area-Efficient XNOR-AND Hybrid Binary Neural Networks Using TFT-Type Synaptic Device IS Lee, H Kim, MK Park, J Hwang, RH Koo, JJ Kim, JH Lee IEEE Electron Device Letters 44 (2), 325-328, 2022 | 1 | 2022 |
| CRUS: A Hardware-Efficient Algorithm Mitigating Highly Nonlinear Weight Update in CIM Crossbar Arrays for Artificial Neural Networks J Lee, J Hwang, Y Cho, MK Park, WY Choi, S Kim, JH Lee IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 8 …, 2022 | 1 | 2022 |
| Synaptic array structure based on cmos integration technology and method of fabricating the synaptic array structure J Lee, MK Park, J Hwang, GU Ryunhan, WM Kang US Patent App. 18/488,916, 2024 | | 2024 |
| NOR-type Flash Array Based on Four-terminal TFT Synaptic Devices Capable of Selective Program/Erase Exploiting Fowler-Nordheim Tunneling J Hwang, MK Park, WM Kang, RH Koo, KH Lee, D Kwon, WY Choi, ... IEEE Electron Device Letters, 2024 | | 2024 |
| Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training MK Park, J Hwang, KM Lee, SY Woo, JJ Kim, JH Bae, JH Lee Advanced Electronic Materials, 2300866, 2024 | | 2024 |
| Accurate SPICE Model for Cells With Tube-Type Poly-Si Channel in Cell Strings of Vertical NAND Flash Memory J Hwang, HN Yoo, KH Lee, JW Back, MK Park, Y Yang, WY Choi, JH Lee IEEE Transactions on Electron Devices, 2023 | | 2023 |
| Analysis of GIDL Erase Characteristics in Vertical NAND Flash Memory HN Yoo, Y Yang, MK Park, WY Choi, JH Lee JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 23 (3), 196-201, 2023 | | 2023 |
| Design of Synaptic Driving Circuit for TFT eFlash-Based Processing-In-Memory Hardware Using Hybrid Bonding Y Kim, H Jin, D Kim, P Ha, MK Park, J Hwang, J Lee, JM Woo, J Choi, ... Electronics 12 (3), 678, 2023 | | 2023 |
| String Current Compensation Method in VNAND Flash for Hardware-Based BNNs JW Back, HN Yoo, J Kim, MK Park, WY Choi, JH Lee IEEE Transactions on Electron Devices 69 (12), 6717-6721, 2022 | | 2022 |
| Awareness Training of Neuron Device with Al₂O₃/Si₃N₄ as a Gate Insulator Stack JH Kim, D Kwon, J Kim, MK Park, H Joon, RH Koo, SW Kim, JH Lee, ... 대한전자공학회 학술대회, 492-493, 2022 | | 2022 |
