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David Kung
David Kung
在 us.ibm.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
Three dimensional integrated circuit
SM Alam, IM Elfadel, KW Guarini, M Ieong, PN Kudva, DS Kung, MA Lavin, ...
US Patent 7,312,487, 2007
2852007
Three dimensional integrated circuit
SM Alam, IM Elfadel, KW Guarini, M Ieong, PN Kudva, DS Kung, MA Lavin, ...
US Patent 7,312,487, 2007
2852007
Pushing ASIC performance in a power envelope
R Puri, L Stok, J Cohn, D Kung, D Pan, D Sylvester, A Srivastava, ...
Proceedings of the 40th annual Design Automation Conference, 788-793, 2003
2122003
Three dimensional integrated circuit and method of design
SM Alam, IM Elfadel, KW Guarini, M Ieong, PN Kudva, DS Kung, MA Lavin, ...
US Patent 7,723,207, 2010
2072010
Three dimensional integrated circuit and method of design
SM Alam, IM Elfadel, KW Guarini, M Ieong, PN Kudva, DS Kung, MA Lavin, ...
US Patent 7,723,207, 2010
2072010
Timing-driven global placement based on geometry-aware timing budgets
JD Cho, DS Kung
US Patent 6,480,991, 2002
1492002
Timing-driven global placement based on geometry-aware timing budgets
JD Cho, DS Kung
US Patent 6,480,991, 2002
1492002
Integrated circuit logic with self compensating block delays
P Gupta, FL Heng, DS Kung, DL Ostapko
US Patent 7,084,476, 2006
1102006
Integrated circuit logic with self compensating block delays
P Gupta, FL Heng, DS Kung, DL Ostapko
US Patent 7,084,476, 2006
1102006
Booledozer: Logic synthesis for asics
L Stok, DS Kung, D Brand, AD Drumm, AJ Sullivan, LN Reddy, N Hieter, ...
IBM Journal of Research and Development 40 (4), 407-430, 1996
971996
An integrated environment for technology closure of deep-submicron IC designs
L Trevillyan, D Kung, R Puri, LN Reddy, MA Kazda
IEEE Design & Test of Computers 21 (1), 14-22, 2004
922004
Hazard-non-increasing gate-level optimization algorithms
DS Kung
ICCAD 92, 631-634, 1992
901992
Powerai ddl
M Cho, U Finkler, S Kumar, D Kung, V Saxena, D Sreedhar
arXiv preprint arXiv:1708.02188, 2017
682017
Gate-size selection for standard cell libraries
F Beeftink, P Kudva, D Kung, L Stok
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1998
611998
Clock tree distribution generation by determining allowed placement regions for clocked elements
WR Migatz, PM Campbell, DJ Hathaway, DS Kung, R Puri, LH Trevillyan
US Patent 7,225,421, 2007
512007
Clock tree distribution generation by determining allowed placement regions for clocked elements
WR Migatz, PM Campbell, DJ Hathaway, DS Kung, R Puri, LH Trevillyan
US Patent 7,225,421, 2007
512007
Blueconnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy
M Cho, U Finkler, D Kung, H Hunter
Proceedings of Machine Learning and Systems 1, 241-251, 2019
472019
Minimizing power with flexible voltage islands
R Puri, D Kung, L Stok
2005 IEEE International Symposium on Circuits and Systems, 21-24, 2005
462005
A fast fanout optimization algorithm for near-continuous buffer libraries
DS Kung
Proceedings 1998 Design and Automation Conference. 35th DAC.(Cat. No …, 1998
401998
Optimal P/N width ratio selection for standard cell libraries
DS Kung, R Puri
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999
361999
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