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Byongchan Lim
Byongchan Lim
Apple Inc
Verified email at alumni.stanford.edu
Title
Cited by
Cited by
Year
Fortifying analog models with equivalence checking and coverage analysis
M Horowitz, M Jeeradit, F Lau, S Liao, BC Lim, J Mao
Proceedings of the 47th Design Automation Conference, 425-430, 2010
322010
Digital analog design: Enabling mixed-signal system validation
BC Lim, JE Jang, J Mao, J Kim, M Horowitz
IEEE Design & Test 32 (1), 44-52, 2014
272014
Leveraging designer's intent: A path toward simpler analog CAD tools
J Kim, M Jeeradit, B Lim, MA Horowitz
2009 IEEE Custom Integrated Circuits Conference, 613-620, 2009
232009
Error control and limit cycle elimination in event-driven piecewise linear analog functional models
BC Lim, M Horowitz
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (1), 23-33, 2016
192016
An efficient test vector generation for checking analog/mixed-signal functional models
BC Lim, J Kim, MA Horowitz
Proceedings of the 47th Design Automation Conference, 767-772, 2010
192010
An analog model template library: Simplifying chip-level, mixed-signal design verification
BC Lim, M Horowitz
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 193-204, 2018
182018
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture
S Ji, J Pu, BC Lim, M Horowitz
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016
142016
High speed line equalizer and method thereof
BC Lim, K Hong
US Patent 7,526,043, 2009
142009
Fast FPGA emulation of analog dynamics in digitally-driven systems
S Herbst, BC Lim, M Horowitz
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
82018
20-GS/s 8-bit analog-to-digital converter and 5-GHz phase interpolator for open-source synthesizable high-speed link applications
SJ Kim, Z Myers, S Herbst, B Lim, M Horowitz
IEEE Solid-State Circuits Letters 3, 518-521, 2020
72020
Open-source synthesizable analog blocks for high-speed link designs: 20-GS/s 5b ENOB analog-to-digital converter and 5-GHz phase interpolator
SJ Kim, Z Myers, S Herbst, BC Lim, M Horowitz
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
72020
A digital PLL with 5-phase digital PFD for low long-term jitter clock recovery
TY Oh, SH Yi, S Yang, B Lim, K Hong
IEEE Custom Integrated Circuits Conference 2006, 745-748, 2006
72006
42.2: 1.8‐inch Full‐Color OEL Display for IMT2000 Terminals
YS Na, BC Lim, OK Kwon, CJ Kim, YH Nam, HS Kim, ST Kim
SID Symposium Digest of Technical Papers 33 (1), 1178-1181, 2002
42002
Model Validation of Mixed-Signal Systems
BC Lim
Stanford University, 2012
32012
Digital Analog Design
M Horowitz, M Jeeradit, F Lau, S Liao, BC Lim, J Mao
Workshop on Frontiers in Analog Circuit Synthesis and Verification, 2011
32011
A 220pJ/pixel/frame CMOS Image Sensor with ParHal Se ling Readout Architecture
S Ji, J Pu, BC Lim, M Horowitz
2015
A Wide Operating Frequency Range Delay-Locked Loop Using a Recursive D/A Converter
B Lim, I Jo, D Park, K Hong
2006 Proceedings of the 32nd European Solid-State Circuits Conference, 456-459, 2006
2006
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Articles 1–17