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Nam Sung Kim
Nam Sung Kim
Senior Director, Applied Materials
Verified email at amat.com - Homepage
Title
Cited by
Cited by
Year
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ...
2008 symposium on vlsi technology, 88-89, 2008
1302008
Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration
H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ...
2017 IEEE international electron devices meeting (IEDM), 37.4. 1-37.4. 4, 2017
1222017
Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced vertical nanowires separation, new work function metal gate solutions, and DC/AC performance …
R Ritzenthaler, H Mertens, V Pena, G Santoro, A Chasin, K Kenis, ...
2018 IEEE International Electron Devices Meeting (IEDM), 21.5. 1-21.5. 4, 2018
812018
Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications
BS Wood, MG Ward, S Sun, M Chudzik, NS Kim, H Chung, YC Huang, ...
US Patent App. 15/395,928, 2017
722017
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
F Arnaud, A Thean, M Eller, M Lipinski, YW Teh, M Ostermayr, K Kang, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
672009
Scaling of 32nm low power SRAM with high-K metal gate
HS Yang, R Wong, R Hasumi, Y Gao, NS Kim, DH Lee, S Badrudduza, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
662008
Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes
CN Ni, KV Rao, F Khaja, S Sharma, S Tang, JJ Chen, KE Hollar, N Breil, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
382016
Horizontal gate all around and FinFET device isolation
S Sun, N Yoshida, TK Guarini, SW Jun, P Vanessa, EAC Sanchez, ...
US Patent 9,865,735, 2018
372018
Asymmetric channel MOSFET
X Chen, J Deng, W Li, DR Nair, JE Park, D Tekleab, X Yuan, NS Kim
US Patent 8,237,197, 2012
332012
Horizontal gate all around device nanowire air gap spacer formation
S Sun, NS Kim, BS Wood, N Yoshida, SC Kung, M Jin
US Patent 10,777,650, 2020
302020
Methods of forming a FinFET semiconductor device by performing an epitaxial growth process
MH Chi, NS Kim
US Patent 8,815,659, 2014
302014
High performance bulk planar 20nm CMOS technology for low power mobile applications
H Shang, S Jain, E Josse, E Alptekin, MH Nam, SW Kim, KH Cho, I Kim, ...
2012 Symposium on VLSI Technology (VLSIT), 129-130, 2012
302012
Selective atomic layer deposition of MoSix on Si (0 0 1) in preference to silicon nitride and silicon oxide
JY Choi, CF Ahles, R Hung, N Kim, AC Kummel
Applied Surface Science 462, 1008-1016, 2018
232018
Si/SiGe superlattice I/O FinFETs in a vertically-stacked gate-all-around horizontal nanowire technology
G Hellings, H Mertens, A Subirats, E Simoen, T Schram, LA Ragnarsson, ...
2018 IEEE Symposium on VLSI Technology, 85-86, 2018
222018
Methods for fabricating nanowire for semiconductor applications
KT Wong, S Sun, SS Kang, NS Kim, SD Nemani, EY Yieh
US Patent 10,269,571, 2019
202019
Method for fabricating junctions and spacers for horizontal gate all around devices
N Yoshida, L Dong, S Sun, M Kim, NS Kim, D Kioussis, M Korolik, ...
US Patent 10,177,227, 2019
152019
New layout dependency in high-k/metal gate MOSFETs
M Hamaguchi, D Nair, D Jaeger, H Nishimura, W Li, MH Na, C Bernicot, ...
2011 International Electron Devices Meeting, 25.6. 1-25.6. 4, 2011
122011
Highly conductive metal gate fill integration solution for extremely scaled RMG stack for 5 nm & beyond
N Yoshida, S Hassan, W Tang, Y Yang, W Zhang, SC Chen, L Dong, ...
2017 IEEE International Electron Devices Meeting (IEDM), 22.2. 1-22.2. 4, 2017
112017
PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond
CN Ni, YC Huang, S Jun, S Sun, A Vyas, F Khaja, KV Rao, S Sharma, ...
2016 International Symposium on VLSI Technology, Systems and Application …, 2016
112016
Extreme contact scaling with advanced metallization of cobalt
R Hung, JH Park, TH Ha, M Lee, W Hou, J Lei, JR Bakke, S Sharma, ...
2018 IEEE International Interconnect Technology Conference (IITC), 30-32, 2018
102018
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