| Nanosheet transistor with improved inner spacer R Xie, K Cheng, N Loubet, X Miao, P Montanini, J Zhang, H Huang, ... US Patent App. 15/703,221, 2019 | 31 | 2019 |
| Multi-phase source/drain/gate spacer-epi formation P Jianwei, X Wu, H Yu, Z Lun US Patent 9,337,306, 2016 | 31 | 2016 |
| Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors JW Peng, SJ Lee, GC Liang, N Singh, SY Zhu, GQ Lo, DL Kwong Applied Physics Letters 93 (7), 2008 | 31 | 2008 |
| CMOS compatible Ge/Si core/shell nanowire gate-all-around pMOSFET integrated with HfO2/TaN gate stack JW Peng, N Singh, GQ Lo, DL Kwong, SJ Lee Proc. IEEE Int. Devices Meeting, 38.32, 2009 | 22 | 2009 |
| In-Situ Boron Doped SiGe Epitaxy Optimization for FinFET Source/Drain Yi Qi, Jianwei Peng, Hsien-Ching Lo, Judson Robert Holt, Michael Willemann ... ECS Transactions 75 (8), 265-272, 2016 | 20 | 2016 |
| Germanium nanowire metal–oxide–semiconductor field-effect transistor fabricated by complementary-metal–oxide–semiconductor-compatible process JW Peng, N Singh, GQ Lo, M Bosman, CM Ng, SJ Lee IEEE transactions on electron devices 58 (1), 74-79, 2010 | 14 | 2010 |
| Source/drain eSiGe engineering for FinFET technology J Peng, Y Qi, HC Lo, P Zhao, C Yong, J Yan, X Dou, H Zhan, Y Shen, ... Semiconductor Science and Technology 32 (9), 094004, 2017 | 13 | 2017 |
| Hybrid low‐k spacer scheme for advanced FinFET technology parasitic capacitance reduction M Gu, X Wang, W Li, M Aquilino, J Peng, H Wang, D Jaeger, K Tabakman, ... Electronics Letters 56 (10), 514-516, 2020 | 12 | 2020 |
| Multi-layer spacer used in finFET P Jianwei, H Yu, Z Lun, T Han, HC Lo, B Banerjee, WZ Gao, ... US Patent 9,419,101, 2016 | 11 | 2016 |
| A 12nm FinFET technology featuring 2nd generation FinFET for low power and high performance applications HC Lo, D Choi, Y Hu, Y Shen, Y Qi, J Peng, D Zhou, M Mohan, C Yong, ... 2018 IEEE Symposium on VLSI Technology, 215-216, 2018 | 10 | 2018 |
| FinFET conformal junction and high EPI surface dopant concentration method and device P Feng, P Jianwei, Y Liu, SM Pandey, F Benistant US Patent 9,406,752, 2016 | 10 | 2016 |
| Metal-insulator-metal capacitors with enlarged contact areas S Gu, P Jianwei, X Wu, Y Qi, J Chee US Patent 10,446,483, 2019 | 9 | 2019 |
| Method of forming a vertical field effect transistor (VFET) and a VFET structure Y Qi, P Jianwei, HC Lo, R Xie, X Zhang, H Zang US Patent 10,276,689, 2019 | 9 | 2019 |
| Multiple gate length device with self-aligned top junction H Zang, P Jianwei, Y Qi, HC Lo, J Ciavatti, R Xie US Patent 10,410,929, 2019 | 8 | 2019 |
| Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device Y Qi, HC Lo, P Jianwei, S Yanping, H Zhan US Patent 9,887,094, 2018 | 8 | 2018 |
| Multiple-layer spacers for field-effect transistors T Han, Z Hu, J Liu, HC Lo, P Jianwei US Patent 9,947,769, 2018 | 7 | 2018 |
| Introducing material with a lower etch rate to form a t-shaped sdb sti structure P Jianwei, X Wu US Patent App. 15/078,247, 2017 | 7 | 2017 |
| Abnormal silicon-germanium (SiGe) epitaxial growth in FinFETs TS Bhat, S Shintri, B Chen, HC Lo, J Peng, Y Qi, M Willeman, SK Mishra, ... IEEE Transactions on Semiconductor Manufacturing 33 (2), 291-294, 2020 | 5 | 2020 |
| A novel approach to control source/drain cavity profile for device performance improvement HC Lo, J Peng, E Reis, B Zhu, W Ma, SY Mun, S Shintri, EM Bazizi, ... IEEE Transactions on Electron Devices 65 (9), 3640-3645, 2018 | 5 | 2018 |
| Dual-curvature cavity for epitaxial semiconductor growth A Vinslava, HC Lo, Y Shi, P Jianwei, J Yan, Y Qi US Patent 10,297,675, 2019 | 4 | 2019 |
Yi QiAssociate Professor and Chair, Department of Transportation Studies, Texas Southern UniversityVerified email at tsu.edu
