| VLSI test principles and architectures: design for testability LT Wang, CW Wu, X Wen Elsevier, 2006 | 884 | 2006 |
| Power-aware testing and test strategies for low power devices P Girard, N Nicolici, X Wen Springer Science & Business Media, 2010 | 281 | 2010 |
| On low-capture-power test generation for scan testing X Wen, Y Yamashita, S Kajihara, LT Wang, KK Saluja, K Kinoshita 23rd IEEE VLSI Test Symposium (VTS'05), 265-270, 2005 | 225 | 2005 |
| Low-capture-power test generation for scan-based at-speed testing X Wen, Y Yamashita, S Morishima, S Kajihara, LT Wang, KK Saluja, ... IEEE International Conference on Test, 2005., 10 pp.-1028, 2005 | 173 | 2005 |
| Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques MT Chang, SH Lin, HJ Chao, J Lee, HP Wang, X Wen, PC Hsu, SC Kao, ... US Patent 7,191,373, 2007 | 138 | 2007 |
| VirtualScan: A new compressed scan technology for test cost reduction LT Wang, X Wen, H Furukawa, FS Hsu, SH Lin, SW Tsai, KS Abdel-Hafez, ... 2004 International Conferce on Test, 916-925, 2004 | 129 | 2004 |
| A new ATPG method for efficient capture power reduction during scan testing X Wen, S Kajihara, K Miyase, T Suzuki, KK Saluja, LT Wang, ... 24th IEEE VLSI Test Symposium, 6 pp.-65, 2006 | 121 | 2006 |
| Computer-aided design system to automate scan synthesis at register-transfer level LT Wang, A Kifli, FS Hsu, SC Kao, X Wen, SH Lin, HP Wang US Patent 6,957,403, 2005 | 110* | 2005 |
| Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits KS Abdel-Hafez, X Wen, LT Wang, PC Hsu, SC Kao, HJ Chao, HP Wang US Patent 7,058,869, 2006 | 103 | 2006 |
| A novel scheme to reduce power supply noise for high-quality at-speed scan testing X Wen, K Miyase, S Kajihara, T Suzuki, Y Yamato, P Girard, Y Ohsumi, ... 2007 IEEE International Test Conference, 1-10, 2007 | 92 | 2007 |
| Mask network design for scan-based integrated circuits SMS Wang, KS Abdel-Hafez, X Wen, BJ Sheu US Patent 7,032,148, 2006 | 84* | 2006 |
| Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing X Wen, K Miyase, T Suzuki, S Kajihara, Y Ohsumi, KK Saluja Proceedings of the 44th annual Design Automation Conference, 527-532, 2007 | 79 | 2007 |
| Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test PC Hsu, SC Kao, MC Lin, HP Wang, HJ Chao, X Wen US Patent 7,007,213, 2006 | 75* | 2006 |
| Multiple-capture DFT system for scan-based integrated circuits MC Lin, X Wen, HP Wang, CC Hsu, SC Kao, FS Hsu US Patent 6,954,887, 2005 | 74 | 2005 |
| Method and system to optimize test cost and disable defects for scan and BIST memories LT Wang, SH Lin, CC Hsu, X Wen, A Vu, Y Park, HP Wang US Patent App. 10/116,128, 2002 | 73 | 2002 |
| Novel low cost, double-and-triple-node-upset-tolerant latch designs for nano-scale CMOS A Yan, C Lai, Y Zhang, J Cui, Z Huang, J Song, J Guo, X Wen IEEE Transactions on Emerging Topics in Computing 9 (1), 520-533, 2018 | 72 | 2018 |
| Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit LT Wang, KS Abdel-Hafez, X Wen, BJ Sheu, FS Hsu, A Kifli, SH Lin, S Wu, ... US Patent 7,512,851, 2009 | 70 | 2009 |
| Method and apparatus for unifying self-test with scan-test during prototype debug and production test X Wen, KS Abdel-Hafez, SH Lin, HP Wang, MT Chang, PC Hsu, SC Kao, ... US Patent 7,444,567, 2008 | 63 | 2008 |
| A highly-guided X-filling method for effective low-capture-power scan test generation X Wen, K Miyase, T Suzuki, Y Yamato, S Kajihara, LT Wang, KK Saluja 2006 International Conference on Computer Design, 251-258, 2006 | 63 | 2006 |
| Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding D Xiang, X Wen, LT Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3), 942-953, 2016 | 61 | 2016 |
