| A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS W Wu, Y Zhu, L Ding, CH Chan, UF Chio, SW Sin, U Seng-Pan, ... Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, 2239-2242, 2013 | 11 | 2013 |
| A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration L Ding, W Wu, SW Sin, U Seng-Pan, RP Martins Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian, 77-80, 2013 | 4 | 2013 |
| A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array W Wu, SW Sin, U Seng-Pan, RP Martins Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on, 268-271, 2012 | 4 | 2012 |
| A linear high gain time difference amplifier using feedback gain control W Wu, RJ Baker, P Bikkina, F Garcia, E Mikkola Circuits and Systems Conference (DCAS), 2016 IEEE Dallas, 1-4, 2016 | 3 | 2016 |
| Design and analysis of a feedback time difference amplifier with linear and programmable gain W Wu, RJ Baker, P Bikkina, Y Long, A Levy, E Mikkola Analog Integrated Circuits and Signal Processing 94, 357-367, 2018 | 2 | 2018 |
| Column-parallel adc architectures for high-speed cmos image sensors W Wu, E Mikkola US Patent App. 17/498,529, 2022 | | 2022 |
| High-Speed Radhard Mega-Pixel CIS Camera for High-Energy Physics W Wu University of Nevada, Las Vegas, 2019 | | 2019 |
| RFI Mitigating Receiver Back-end for Radiometers PK Bikkina, QJ Fan, W Wu, J Chen, E Mikkola IEEE Geoscience and Remote Sensing Symposium, 2017 | | 2017 |
Sai-Weng Sin (Terry)University of MacauVerified email at um.edu.mo
