Sung Kim
Title
Cited by
Cited by
Year
Real-time bidirectional traffic flow parameter estimation from aerial videos
R Ke, Z Li, S Kim, J Ash, Z Cui, Y Wang
IEEE Transactions on Intelligent Transportation Systems 18 (4), 890-901, 2016
1082016
MATIC: Learning around errors for efficient low-voltage neural network accelerators
S Kim, P Howe, T Moreau, A Alaghi, L Ceze, V Sathe
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2018
382018
Energy-efficient neural network acceleration in the presence of bit-level memory errors
S Kim, P Howe, T Moreau, A Alaghi, L Ceze, VS Sathe
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4285-4298, 2018
352018
Motion-vector clustering for traffic speed detection from UAV video
R Ke, S Kim, Z Li, Y Wang
2015 IEEE First International Smart Cities Conference (ISC2), 1-5, 2015
282015
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains
F ur Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ...
IEEE Journal of Solid-State Circuits 54 (4), 1173-1184, 2019
172019
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS
VR Pamula, X Sun, S Kim, F ur Rahman, B Zhang, VS Sathe
2018 IEEE Symposium on VLSI Circuits, 1-2, 2018
162018
Exploring computation-communication tradeoffs in camera systems
A Mazumdar, T Moreau, S Kim, M Cowan, A Alaghi, L Ceze, M Oskin, ...
2017 IEEE International Symposium on Workload Characterization (IISWC), 177-186, 2017
162017
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0 V Cortex-M0 processor
X Sun, S Kim, F ur Rahman, VR Pamula, X Li, N John, VS Sathe
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 302-304, 2018
152018
An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM Cortex M0 processor
FU Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ...
2018 IEEE Symposium on VLSI Circuits, 65-66, 2018
112018
Bandwidth Extension on Raw Audio via Generative Adversarial Networks
S Kim, V Sathe
arXiv preprint arXiv:1903.09027, 2019
10*2019
Transmuter: Bridging the efficiency gap using memory and dataflow reconfiguration
S Pal, S Feng, D Park, S Kim, A Amarnath, CS Yang, X He, J Beaumont, ...
Proceedings of the ACM International Conference on Parallel Architectures …, 2020
62020
An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
X Sun, F ur Rahman, VR Pamula, S Kim, X Li, N John, VS Sathe
IEEE Journal of Solid-State Circuits 54 (11), 3215-3225, 2019
62019
A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction
VR Pamula, X Sun, SM Kim, F ur Rahman, B Zhang, VS Sathe
IEEE Solid-State Circuits Letters 1 (12), 237-240, 2018
52018
Enabling time-critical applications over next-generation 802.11 networks
S Kim, MM Rashid, S Deo, J Perez-Ramirez, M Galeev, G Venkatesan, ...
IEEE INFOCOM 2018-IEEE Conference on Computer Communications Workshops …, 2018
22018
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
S Kim, M Fayazi, A Daftardar, KY Chen, J Tan, S Pal, T Ajayi, Y Xiong, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
12021
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