| A definition and classification of timing anomalies J Reineke, B Wachter, S Thesing, R Wilhelm, I Polian, J Eisinger, ... 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06), 2006 | 276 | 2006 |
| A family of logical fault models for reversible circuits I Polian, T Fiehn, B Becker, JP Hayes 14th Asian Test Symposium (ATS'05), 422-427, 2005 | 148 | 2005 |
| Testing for missing-gate faults in reversible circuits JP Hayes, I Polian, B Becker 13th Asian test symposium, 100-105, 2004 | 136 | 2004 |
| X-masking during logic BIST and its impact on defect coverage Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ... 2004 International Conferce on Test, 442-451, 2004 | 129 | 2004 |
| Simulating resistive-bridging and stuck-at faults P Engelke, I Polian, M Renovell, B Becker IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 102 | 2006 |
| Parametric trojans for fault-injection attacks on cryptographic hardware R Kumar, P Jovanovic, W Burleson, I Polian 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 18-28, 2014 | 82 | 2014 |
| A fault attack on the LED block cipher P Jovanovic, M Kreuzer, I Polian Constructive Side-Channel Analysis and Secure Design: Third International …, 2012 | 81 | 2012 |
| Adaptive voltage over-scaling for resilient applications PK Krause, I Polian 2011 Design, Automation & Test in Europe, 1-6, 2011 | 80 | 2011 |
| An analysis framework for transient-error tolerance JP Hayes, I Polian, B Becker 25th IEEE VLSI Test Symposium (VTS'07), 249-255, 2007 | 78 | 2007 |
| Power droop testing I Polian, A Czutro, S Kundu, B Becker 2006 International Conference on Computer Design, 243-250, 2006 | 75 | 2006 |
| Fault-tolerant, high-level quantum circuits: form, compilation and description A Paler, I Polian, K Nemoto, SJ Devitt Quantum Science and Technology 2 (2), 025003, 2017 | 71 | 2017 |
| Analysis and optimization of fault-tolerant embedded systems with hardened processors V Izosimov, I Polian, P Pop, P Eles, Z Peng 2009 Design, Automation & Test in Europe Conference & Exhibition, 682-687, 2009 | 71 | 2009 |
| Selective hardening: Toward cost-effective error tolerance I Polian, JP Hayes IEEE Design & Test of Computers 28 (3), 54-63, 2010 | 66 | 2010 |
| A simulator of small-delay faults caused by resistive-open defects A Czutro, N Houarche, P Engelke, I Polian, M Comte, M Renovell, ... 2008 13th European Test Symposium, 113-118, 2008 | 66 | 2008 |
| Small-delay-fault ATPG with waveform accuracy M Sauer, A Czutro, I Polian, B Becker Proceedings of the International Conference on Computer-Aided Design, 30-36, 2012 | 60 | 2012 |
| Functional constraints vs. test compression in scan-based delay testing I Polian, H Fujiwara Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 60 | 2006 |
| Automatic test pattern generation for interconnect open defects S Spinner, I Polian, P Engelke, B Becker, M Keim, WT Cheng 26th IEEE VLSI Test Symposium (vts 2008), 181-186, 2008 | 58 | 2008 |
| Resistive bridge fault model evolution from conventional to ultra deep submicron I Polian, P Engelke, B Becker, S Kundu, JM Galliere, M Renovell 23rd IEEE VLSI Test Symposium (VTS'05), 343-348, 2005 | 58 | 2005 |
| Selective hardening in early design steps CG Zoellin, HJ Wunderlich, I Polian, B Becker 2008 13th European test symposium, 185-190, 2008 | 53 | 2008 |
| Modeling and mitigating transient errors in logic circuits I Polian, JP Hayes, SM Reddy, B Becker IEEE Transactions on Dependable and Secure Computing 8 (4), 537-547, 2011 | 52 | 2011 |
Bernd BeckerProfessor of Computer Science, University of Freiburg在 informatik.uni-freiburg.de 的电子邮件经过验证
