| Survey of low-power testing of VLSI circuits P Girard IEEE Design & test of computers 19 (3), 82-92, 2002 | 648 | 2002 |
| Observation of exclusive deeply virtual Compton scattering in polarized electron beam asymmetry measurements S Stepanyan, VD Burkert, L Elouadrhiri, GS Adams, E Anciant, ... Physical Review Letters 87 (18), 182002, 2001 | 502 | 2001 |
| Power-aware testing and test strategies for low power devices P Girard, N Nicolici, X Wen Springer Science & Business Media, 2010 | 281 | 2010 |
| A test vector inhibiting technique for low energy BIST design P Girard, L Guiller, C Landrault, S Pravossoudovitch Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 407-412, 1999 | 234 | 1999 |
| A modified clock scheme for a low power BIST test pattern generator P Girard, L Guiller, C Landrault, S Pravossoudovitch, HJ Wunderlich Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 306-311, 2001 | 201 | 2001 |
| A gated clock scheme for low power scan testing of logic ICs or embedded cores Y Bonhomme, P Girard, L Guiller, C Landrault, S Pravossoudovitch Proceedings 10th Asian Test Symposium, 253-258, 2001 | 195 | 2001 |
| Reducing power consumption during test application by test vector ordering P Girard, C Landrault, S Pravossoudovitch, D Severac 1998 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 296-299, 1998 | 174 | 1998 |
| Quaternions PR Girard Quaternions, Clifford Algebras and Relativistic Physics, 3-17, 2007 | 156 | 2007 |
| Power driven chaining of flip-flops in scan architectures Y Bonhomme, P Girard, C Landrault, S Pravossoudovitch Proceedings. International Test Conference, 796-803, 2002 | 135 | 2002 |
| A test vector ordering technique for switching activity reduction during test operation P Girard, L Guiller, C Landrault, S Pravossoudovitch Proceedings Ninth Great Lakes Symposium on VLSI, 24-27, 1999 | 121 | 1999 |
| Low power testing of VLSI circuits: Problems and solutions P Girard Proceedings IEEE 2000 First International Symposium on Quality Electronic …, 2000 | 116 | 2000 |
| Low-energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity P Girard, L Guiller, C Landrault, S Pravossoudovitch, J Figueras, ... 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 110-113, 1999 | 104 | 1999 |
| Efficient scan chain design for power minimization during scan testing under routing constraint Y Bonhomme, P Girard, L Guiller, C Landrault, S Pravossoudovitch ITC: International Test Conference, 488-493, 2003 | 96 | 2003 |
| Advanced test methods for SRAMs: effective solutions for dynamic fault detection in Nanoscaled technologies A Bosio, L Dilillo, P Girard, S Pravossoudovitch, A Virazel Springer Science & Business Media, 2009 | 95* | 2009 |
| Low power BIST by filtering non-detecting vectors S Manich, A Gabarro, M Lopez, J Figueras, P Girard, L Guiller, ... Journal of Electronic Testing 16, 193-202, 2000 | 95 | 2000 |
| A novel scheme to reduce power supply noise for high-quality at-speed scan testing X Wen, K Miyase, S Kajihara, T Suzuki, Y Yamato, P Girard, Y Ohsumi, ... 2007 IEEE International Test Conference, 1-10, 2007 | 92 | 2007 |
| A study of tapered 3-D TSVs for power and thermal integrity A Todri, S Kundu, P Girard, A Bosio, L Dilillo, A Virazel IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 306-319, 2012 | 89 | 2012 |
| Circuit partitioning for low power BIST design with minimized peak power consumption P Girard, L Guiller, C Landrault, S Pravossoudovitch Proceedings Eighth Asian Test Symposium (ATS'99), 89-94, 1999 | 87 | 1999 |
| Resistive-open defects in embedded-SRAM core cells: analysis and march test solution L Dilillo, P Girard, S Pravossoudovitch, A Virazel, S Borri, M Hage-Hassan 13th Asian test symposium, 266-271, 2004 | 85 | 2004 |
| Dynamic Read Destructive Faults in Embedded-SRAMs: Analysis and March Test Solution L Dilillo, P Girard, S Pravossoudovitch, A Virazel, S Borri, M Hage-Hassan ETS: European Test Symposium, 140-145, 2004 | 85 | 2004 |
