Sheng Li
Cited by
Cited by
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures
NPJ Sheng Li, Jung Ho Ahn, Richard D Strong, Jay B Brockman, Dean M Tullsen
Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International …, 2009
Kiln: Closing the performance gap between systems with and without persistence support
J Zhao, S Li, DH Yoon, Y Xie, NP Jouppi
Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques
S Li, K Chen, JH Ahn, JB Brockman, NP Jouppi
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 694-701, 2011
CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory
K Chen, S Li, N Muralimanohar, JH Ahn, JB Brockman, NP Jouppi
Faster cnns with direct sparse convolutions and guided pruning
J Park, S Li, W Wen, PTP Tang, H Li, Y Chen, P Dubey
arXiv preprint arXiv:1608.01409, 2016
Architecting to achieve a billion requests per second throughput on a single key-value store server platform
S Li, H Lim, VW Lee, JH Ahn, A Kalia, M Kaminsky, DG Andersen, ...
Proceedings of the 42nd Annual International Symposium on Computer …, 2015
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling
JH Ahn, S Li, O Seongil, NP Jouppi
2013 IEEE International Symposium on Performance Analysis of Systems and …, 2013
System implications of memory reliability in exascale computing
S Li, K Chen, MY Hsieh, N Muralimanohar, CD Kersey, JB Brockman, ...
SC'11: Proceedings of 2011 International Conference for High Performance …, 2011
Performing power management in a multicore processor
VW Lee, ET Grochowski, D Kim, Y Bai, S Li, NK Mellempudi, ...
US Patent 10,234,930, 2019
Parallelizing word2vec in shared and distributed memory
S Ji, N Satish, S Li, PK Dubey
IEEE Transactions on Parallel and Distributed Systems 30 (9), 2090-2100, 2019
A domain-specific supercomputer for training deep neural networks
NP Jouppi, DH Yoon, G Kurian, S Li, N Patil, J Laudon, C Young, ...
Communications of the ACM 63 (7), 67-78, 2020
System-level integrated server architectures for scale-out datacenters
S Li, K Lim, P Faraboschi, J Chang, P Ranganathan, NP Jouppi
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
MAGE: adaptive granularity and ECC for resilient and power efficient memory systems
S Li, DH Yoon, K Chen, J Zhao, JH Ahn, JB Brockman, Y Xie, NP Jouppi
Proceedings of the International Conference on High Performance Computing …, 2012
Enabling sparse winograd convolution by native pruning
S Li, J Park, PTP Tang
arXiv preprint arXiv:1702.08597, 2017
Memory network with memory nodes controlling memory accesses in the memory network
S Li, NP Jouppi, P Faraboschi, MR Krause
US Patent 10,572,150, 2020
Methods and apparatus to perform error detection and correction
S Li, NP Jouppi, N Muralimanohar
US Patent 8,788,904, 2014
黄令龙, 郭阳宽, 蒋培军, 李晟, 李庆祥, 陈张玮
清华大学学报: 自然科学版 44 (8), 1054-1056, 2004
Separate memory controllers to access data in memory
DH Yoon, S Li, J Chang, K Chen, P Ranganathan, NP Jouppi
US Patent 10,691,344, 2020
Buri: Scaling big-memory computing with hardware-based memory expansion
J Zhao, S Li, J Chang, JL Byrne, LL Ramirez, K Lim, Y Xie, P Faraboschi
ACM Transactions on Architecture and Code Optimization (TACO) 12 (3), 1-24, 2015
Memory network to route memory traffic and I/O traffic
DL Barron, P Faraboschi, NP Jouppi, MR Krause, S Li
US Patent 9,952,975, 2018
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