| Vertically stacked thin triboelectric nanogenerator for wind energy harvesting ML Seol, JH Woo, SB Jeon, D Kim, SJ Park, J Hur, YK Choi Nano Energy 14, 201-208, 2015 | 193 | 2015 |
| Nature-replicated nano-in-micro structures for triboelectric energy harvesting. ML Seol, JH Woo, DI Lee, H Im, J Hur, YK Choi Small (Weinheim an der Bergstrasse, Germany) 10 (19), 3887-3894, 2014 | 185 | 2014 |
| First demonstration of a logic-process compatible junctionless ferroelectric FinFET synapse for neuromorphic applications M Seo, MH Kang, SB Jeon, H Bae, J Hur, BC Jang, S Yun, S Cho, WK Kim, ... IEEE Electron Device Letters 39 (9), 1445-1448, 2018 | 138 | 2018 |
| Comprehensive analysis of gate-induced drain leakage in vertically stacked nanowire FETs: Inversion-mode versus junctionless mode J Hur, BH Lee, MH Kang, DC Ahn, T Bang, SB Jeon, YK Choi IEEE Electron Device Letters 37 (5), 541-544, 2016 | 82 | 2016 |
| A vertically integrated junctionless nanowire transistor BH Lee, J Hur, MH Kang, T Bang, DC Ahn, D Lee, KH Kim, YK Choi Nano letters 16 (3), 1840-1847, 2016 | 75 | 2016 |
| Vertically integrated multiple nanowire field effect transistor BH Lee, MH Kang, DC Ahn, JY Park, T Bang, SB Jeon, J Hur, D Lee, ... Nano Letters 15 (12), 8056-8061, 2015 | 70 | 2015 |
| Direct comparison of ferroelectric properties in Hf0.5Zr0.5O2 between thermal and plasma-enhanced atomic layer deposition J Hur, N Tasneem, G Choe, P Wang, Z Wang, AI Khan, S Yu Nanotechnology, 2020 | 53 | 2020 |
| All‐Solid‐State Ion Synaptic Transistor for Wafer‐Scale Integration with Electrolyte of a Nanoscale Thickness JM Yu, C Lee, DJ Kim, H Park, JK Han, J Hur, JK Kim, MS Kim, M Seo, ... Advanced Functional Materials, 2010971, 2021 | 44 | 2021 |
| Drain–erase scheme in ferroelectric field-effect transistor—Part I: Device characterization P Wang, Z Wang, W Shim, J Hur, S Datta, AI Khan, S Yu IEEE Transactions on Electron Devices 67 (3), 955-961, 2020 | 38 | 2020 |
| Drain-erase scheme in ferroelectric field effect transistor—Part II: 3-D-NAND architecture for in-memory computing P Wang, W Shim, Z Wang, J Hur, S Datta, AI Khan, S Yu IEEE Transactions on Electron Devices 67 (3), 962-967, 2020 | 37 | 2020 |
| A Recoverable Synapse Device Using a Three‐Dimensional Silicon Transistor J Hur*, BC Jang*, J Park, DI Moon, H Bae, JY Park, GH Kim, SB Jeon, ... Advanced Functional Materials 28 (47), 1804844, 2018 | 37 | 2018 |
| Antiferroelectric negative capacitance from a structural phase transition in zirconia M Hoffmann, Z Wang, N Tasneem, A Zubair, PV Ravindran, M Tian, ... Nature communications 13 (1), 1228, 2022 | 27 | 2022 |
| Ferroelectric HfO2-based synaptic devices: recent trends and prospects S Yu, J Hur, YC Luo, W Shim, G Choe, P Wang Semiconductor Science and Technology 36 (10), 104001, 2021 | 27 | 2021 |
| Ferroelectric hafnium zirconium oxide compatible with back-end-of-line process J Hur, YC Luo, N Tasneem, AI Khan, S Yu IEEE Transactions on Electron Devices 68 (7), 3176-3180, 2021 | 26 | 2021 |
| Investigating ferroelectric minor loop dynamics and history effect—Part I: Device characterization P Wang, Z Wang, X Sun, J Hur, S Datta, AI Khan, S Yu IEEE Transactions on Electron Devices 67 (9), 3592-3597, 2020 | 26 | 2020 |
| Design of non-volatile capacitive crossbar array for in-memory computing YC Luo, A Lu, J Hur, S Li, S Yu 2021 IEEE International Memory Workshop (IMW), 1-4, 2021 | 25 | 2021 |
| A frequency reconfigurable dipole antenna with solid-state plasma in silicon DJ Kim, ES Jo, YK Cho, J Hur, CK Kim, CH Kim, B Park, D Kim, YK Choi Scientific reports 8 (1), 14996, 2018 | 24 | 2018 |
| The impacts of ferroelectric and interfacial layer thicknesses on ferroelectric FET design N Tasneem, MM Islam, Z Wang, H Chen, J Hur, D Triyoso, S Consiglio, ... IEEE Electron Device Letters 42 (8), 1156-1159, 2021 | 23 | 2021 |
| A comparative study on hot-carrier injection in 5-story vertically integrated inversion-mode and junctionless-mode gate-all-around MOSFETs SY Kim, BH Lee, J Hur, JY Park, SB Jeon, SW Lee, YK Choi IEEE Electron Device Letters 39 (1), 4-7, 2017 | 23 | 2017 |
| Abnormal electrical characteristics of multi-layered MoS2 FETs attributed to bulk traps CK Kim, CH Yu, J Hur, H Bae, SB Jeon, H Park, YM Kim, KC Choi, ... 2D Materials 3 (1), 015007, 2016 | 23 | 2016 |
