| An optimum loop gain tracking all-digital PLL using autocorrelation of bang–bang phase-frequency detection S Jang, S Kim, SH Chu, GS Jeong, Y Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 62 (9), 836-840, 2015 | 62 | 2015 |
| A 22 to 26.5 Gb/s optical receiver with all-digital clock and data recovery in a 65 nm CMOS process SH Chu, W Bae, GS Jeong, S Jang, S Kim, J Joo, G Kim, DK Jeong IEEE Journal of Solid-State Circuits 50 (11), 2603-2612, 2015 | 55 | 2015 |
| A 0.36 pJ/bit, 0.025 mm, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 63 (9), 1393-1403, 2016 | 29 | 2016 |
| A 0.015-mmInductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology GS Jeong, W Kim, J Park, T Kim, H Park, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 64 (6), 655-659, 2015 | 29 | 2015 |
| Review of CMOS integrated circuit technologies for high-speed photo-detection GS Jeong, W Bae, DK Jeong Sensors 17 (9), 1962, 2017 | 27 | 2017 |
| Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~ 1550 nm J Joo, KS Jang, SH Kim, IG Kim, JH Oh, SA Kim, GS Jeong, Y Kim, ... Optics express 23 (9), 12232-12243, 2015 | 26 | 2015 |
| A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-Bias GS Jeong, SH Chu, Y Kim, S Jang, S Kim, W Bae, SY Cho, H Ju, ... IEEE Journal of Solid-State Circuits 51 (10), 2312-2327, 2016 | 22 | 2016 |
| A 32 Gb/s, 201 mW, MZM/EAM cascode push–pull CML driver in 65 nm CMOS J Hwang, GS Jeong, W Bae, JE Park, CS Yoon, JM Yoon, J Joo, G Kim, ... IEEE Transactions on Circuits and Systems II: Express Briefs 65 (4), 436-440, 2017 | 21 | 2017 |
| Design of silicon photonic interconnect ICs in 65-nm CMOS technology W Bae, GS Jeong, Y Kim, HK Chi, DK Jeong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2015 | 20 | 2015 |
| Reference spur reduction techniques for a phase-locked loop HG Ko, W Bae, GS Jeong, DK Jeong IEEE Access 7, 38035-38043, 2019 | 19 | 2019 |
| An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation S Jang, S Kim, SH Chu, GS Jeong, Y Kim, DK Jeong 2015 Symposium on VLSI Circuits (VLSI Circuits), C136-C137, 2015 | 19 | 2015 |
| A 64Gb/s 2.29 pJ/b PAM-4 VCSEL transmitter with 3-tap asymmetric FFE in 65nm CMOS J Hwang, HS Choi, H Do, GS Jeong, D Koh, K Park, S Kim, DK Jeong 2019 Symposium on VLSI Circuits, C268-C269, 2019 | 18 | 2019 |
| A 35-Gb/s 0.65-pJ/b asymmetric push-pull inverter-based VCSEL driver with series inductive peaking in 65-nm CMOS HS Choi, J Hwang, GS Jeong, G Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 1824-1828, 2018 | 14 | 2018 |
| A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and -Regulated Resistive-Feedback Driver H Ju, MC Choi, GS Jeong, W Bae, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 64 (12), 1377-1381, 2017 | 14 | 2017 |
| A 20-Gb/s 1.27 pJ/b low-power optical receiver front-end in 65nm CMOS GS Jeong, H Chi, K Kim, DK Jeong 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1492-1495, 2014 | 13 | 2014 |
| A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm GS Jeong, SH Chu, Y Kim, S Jang, S Kim, W Bae, SY Cho, H Ju, ... 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015 | 12 | 2015 |
| A 1-pJ/bit, 10-Gb/s/ch forwarded-clock transmitter using a resistive feedback inverter-based driver in 65-nm CMOS W Bae, GS Jeong, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 63 (12), 1106-1110, 2016 | 10 | 2016 |
| A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS K Park, W Bae, H Ju, J Lee, GS Jeong, Y Kim, DK Jeong 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2389-2392, 2015 | 9 | 2015 |
| A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 447-450, 2014 | 9 | 2014 |
| 56Gb/s PAM-4 VCSEL transmitter with quarter-rate forwarded clock using 65nm CMOS circuits J Hwang, H Do, HS Choi, GS Jeong, D Koh, S Kim, DK Jeong Optical Fiber Communication Conference, W2A. 1, 2019 | 8 | 2019 |
