| Digital versus analog artificial intelligence accelerators: Advances, trends, and emerging designs J Seo, J Saikia, J Meng, W He, H Suh, Y Liao, A Hasssan, I Yeo IEEE Solid-State Circuits Magazine 14 (3), 65-79, 2022 | 22 | 2022 |
| End-to-end FPGA-based object detection using pipelined CNN and non-maximum suppression A Anupreetham, M Ibrahim, M Hall, A Boutros, A Kuzhively, A Mohanty, ... 2021 31st International Conference on Field-Programmable Logic and …, 2021 | 9 | 2021 |
| High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design A Anupreetham, M Ibrahim, M Hall, A Boutros, A Kuzhively, A Mohanty, ... ACM Transactions on Reconfigurable Technology and Systems 17 (1), 1-20, 2024 | 1 | 2024 |
| 3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression G Krishnan, GR Nair, J Oh, A Anupreetham, PS Nalla, A Hassan, I Yeo, ... 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2023 | 1 | 2023 |
| Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design J Meng, Y Liao, A Anupreetham, A Hasssan, S Yu, H Suh, X Hu, J Seo arXiv preprint arXiv:2405.01775, 2024 | | 2024 |
| 3D In-Sensor Computing for Real-Time DVS Data Compression: 65nm Hardware-Algorithm Co-Design GR Nair, PS Nalla, G Krishnan, J Oh, A Hassan, I Yeo, K Kasichainula, ... IEEE Solid-State Circuits Letters, 2024 | | 2024 |
| PS-IMC: A 2385.7 TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs A Sridharan, J Saikia, F Zhang, J Seo, D Fan IEEE Solid-State Circuits Letters, 2024 | | 2024 |
Jae-sun SeoCornell TechVerified email at cornell.edu
