| Layout decomposition for triple patterning lithography B Yu, K Yuan, D Ding, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 185 | 2015 |
| Double patterning layout decomposition for simultaneous conflict and stitch minimization K Yuan, JS Yang, D Pan Proceedings of the 2009 international symposium on Physical design, 107-114, 2009 | 156 | 2009 |
| BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router M Cho, K Lu, K Yuan, DZ Pan 2007 IEEE/ACM International Conference on Computer-Aided Design, 503-508, 2007 | 139 | 2007 |
| A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography JS Yang, K Lu, M Cho, K Yuan, DZ Pan 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 637-644, 2010 | 83 | 2010 |
| BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability M Cho, K Lu, K Yuan, DZ Pan ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009 | 64 | 2009 |
| E-beam lithography stencil planning and optimization with overlapped characters K Yuan, DZ Pan Proceedings of the 2011 international symposium on Physical design, 151-158, 2011 | 49 | 2011 |
| WISDOM: Wire spreading enhanced decomposition of masks in double patterning lithography K Yuan, DZ Pan 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 32-38, 2010 | 41 | 2010 |
| ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction M Cho, K Yuan, Y Ban, DZ Pan Proceedings of the 45th annual Design Automation Conference, 504-509, 2008 | 38 | 2008 |
| Double patterning lithography friendly detailed routing with redundant via consideration K Yuan, K Lu, DZ Pan Proceedings of the 46th Annual Design Automation Conference, 63-66, 2009 | 34 | 2009 |
| Dealing with IC manufacturability in extreme scaling B Yu, JR Gao, D Ding, Y Ban, J Yang, K Yuan, M Cho, DZ Pan Proceedings of the International Conference on Computer-Aided Design, 240-242, 2012 | 31 | 2012 |
| AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection D Ding, JR Gao, K Yuan, DZ Pan Proceedings of the 48th Design Automation Conference, 795-800, 2011 | 30 | 2011 |
| Manufacturability aware routing in nanometer VLSI DZ Pan, M Cho, K Yuan Foundations and Trends® in Electronic Design Automation 4 (1), 1-97, 2010 | 24 | 2010 |
| E-BLOW: E-beam lithography overlapping aware stencil planning for MCC system B Yu, K Yuan, JR Gao, DZ Pan Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013 | 22 | 2013 |
| ELIAD: Efficient lithography aware detailed routing algorithm with compact and macro post-OPC printability prediction M Cho, K Yuan, Y Ban, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 19 | 2009 |
| Layout optimizations for double patterning lithography DZ Pan, J Yang, K Yuan, M Cho, Y Ban 2009 IEEE 8th International Conference on ASIC, 726-729, 2009 | 16 | 2009 |
| CAD for double patterning lithography DZ Pan, JS Yang, K Yuan, M Cho 2010 IEEE International Conference on Integrated Circuit Design and …, 2010 | 9 | 2010 |
| Lithography friendly routing: From construct-by-correction to correct-by-construction DZ Pan, M Cho, K Yuan, Y Ban 2008 9th International Conference on Solid-State and Integrated-Circuit …, 2008 | 4 | 2008 |
| EBL overlapping aware stencil planning for MCC system B Yu, K Yuan, JR Gao, S Hu, DZ Pan ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (3 …, 2016 | 2 | 2016 |
| VLSI physical design automation for double patterning and emerging lithography K Yuan | | 2010 |
