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Rafal Baranowski
Rafal Baranowski
Robert Bosch GmbH
在 iti.uni-stuttgart.de 的电子邮件经过验证 - 首页
标题
引用次数
引用次数
年份
Fine-grained access management in reconfigurable scan networks
R Baranowski, MA Kochte, HJ Wunderlich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
792015
Reconfigurable scan networks: Modeling, verification, and optimal pattern generation
R Baranowski, MA Kochte, HJ Wunderlich
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (2 …, 2015
552015
Modeling, verification and pattern generation for reconfigurable scan networks
R Baranowski, MA Kochte, HJ Wunderlich
2012 IEEE International Test Conference, 1-9, 2012
532012
Scan pattern retargeting and merging with reduced access time
R Baranowski, MA Kochte, HJ Wunderlich
2013 18th IEEE European Test Symposium (ETS), 1-7, 2013
412013
Access port protection for reconfigurable scan networks
R Baranowski, MA Kochte, HJ Wunderlich
Journal of Electronic Testing 30 (6), 711-723, 2014
342014
Securing access to reconfigurable scan networks
R Baranowski, MA Kochte, HJ Wunderlich
2013 22nd Asian Test Symposium, 295-300, 2013
332013
On-line prediction of NBTI-induced aging rates
R Baranowski, F Firouzi, S Kiamehr, C Liu, M Tahoori, HJ Wunderlich
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 589-592, 2015
262015
Trustworthy reconfigurable access to on-chip infrastructure
MA Kochte, R Baranowski, HJ Wunderlich
2017 International Test Conference in Asia (ITC-Asia), 119-124, 2017
232017
Formal verification of secure reconfigurable scan network infrastructure
MA Kochte, R Baranowski, M Sauer, B Becker, HJ Wunderlich
2016 21th IEEE European Test Symposium (ETS), 1-6, 2016
232016
Synthesis of workload monitors for on-line stress prediction
R Baranowski, A Cook, ME Imhof, C Liu, HJ Wunderlich
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2013
162013
Test strategies for reconfigurable scan networks
MA Kochte, R Baranowski, M Schaal, HJ Wunderlich
2016 IEEE 25th Asian Test Symposium (ATS), 113-118, 2016
152016
Efficient simulation of structural faults for the reliability evaluation at system-level
MA Kochte, CG Zoellin, R Baranowski, ME Imhof, HJ Wunderlich, ...
2010 19th IEEE Asian Test Symposium, 3-8, 2010
152010
Efficient multi-level fault simulation of HW/SW systems for structural faults
R Baranowski, S Di Carlo, N Hatami, ME Imhof, MA Kochte, P Prinetto, ...
Science China Information Sciences 54 (9), 1784-1796, 2011
122011
Complete formal verification of a family of automotive DSPs
R Baranowski, M Trunzer
Proc. Design Verification Conf. Eur.(DVCON-Eur.), 456-485, 2016
92016
Multilevel simulation of nonfunctional properties by piecewise evaluation
N Hatami, R Baranowski, P Prinetto, HJ Wunderlich
ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (4 …, 2014
82014
Reconfigurable scan networks: formal verification, access optimization, and protection
R Baranowski
52014
Efficient system-level aging prediction
N Hatami, R Baranowski, P Prinetto, HJ Wunderlich
2012 17th IEEE European Test Symposium (ETS), 1-6, 2012
52012
Fail-safety in core-based system design
R Baranowski, HJ Wunderlich
2011 IEEE 17th International On-Line Testing Symposium, 276-281, 2011
32011
Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen
M Kochte, R Baranowski, HJ Wunderlich
GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf 2, 83-90, 2008
32008
System reliability evaluation using concurrent multi-level simulation of structural faults
MA Kochte, CG Zoellin, R Baranowski, ME Imhof, HJ Wunderlich, ...
2010 IEEE International Test Conference, 1-1, 2010
12010
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