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Paul Chow
Paul Chow
Professor of Electrical and Computer Engineering, University of Toronto
Verified email at eecg.toronto.edu
Title
Cited by
Cited by
Year
Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency
J Rose, RJ Francis, D Lewis, P Chow
IEEE Journal of Solid-State Circuits 25 (5), 1217-1225, 1990
4531990
OneChip: An FPGA processor with reconfigurable logic
Wittig, Chow
1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, 126-135, 1996
4441996
The multicluster architecture: Reducing cycle time through partitioning
KI Farkas, P Chow, NP Jouppi, Z Vranesic
Proceedings of 30th Annual International Symposium on Microarchitecture, 149-159, 1997
3521997
Fpgas in the cloud: Booting virtualized hardware accelerators with openstack
S Byma, JG Steffan, H Bannazadeh, A Leon-Garcia, P Chow
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014
3172014
The design of an SRAM-based field-programmable gate array. I. Architecture
P Chow, SO Seo, J Rose, K Chung, G Paez-Monzon, I Rahardja
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (2), 191-197, 1999
1841999
Register file design considerations in dynamically scheduled processors
KI Farkas, NP Jouppi, P Chow
Proceedings. Second International Symposium on High-Performance Computer …, 1996
1661996
Memory interfacing and instruction specification for reconfigurable processors
JA Jacob, P Chow
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999
1631999
Exploiting dual data-memory banks in digital signal processors
MAR Saghir, P Chow, CG Lee
ACM SIGOPS Operating Systems Review 30 (5), 234-243, 1996
1561996
The effect of logic block architecture on FPGA performance
S Singh, J Rose, P Chow, D Lewis
IEEE Journal of Solid-State Circuits 27 (3), 281-287, 1992
1541992
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout
P Chow, SO Seo, J Rose, K Chung, G Páez-Monzón, I Rahardja
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 321-330, 1999
1531999
Caffeinated FPGAs: FPGA framework for convolutional neural networks
R DiCecco, G Lacey, J Vasiljevic, P Chow, G Taylor, S Areibi
2016 International Conference on Field-Programmable Technology (FPT), 265-268, 2016
1502016
TMD-MPI: An MPI implementation for multiple processors across multiple FPGAs
M Saldana, P Chow
2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006
1322006
The effect of reconfigurable units in superscalar processors
JE Carrillo, P Chow
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field …, 2001
1312001
Reconfigurable molecular dynamics simulator
N Azizi, I Kuon, A Egier, A Darabiha, P Chow
12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines …, 2004
1202004
Memory-system design considerations for dynamically-scheduled processors
KI Farkas, P Chow, NP Jouppi, Z Vranesic
ACM SIGARCH Computer Architecture News 25 (2), 133-143, 1997
1171997
MIPS-X: A 20-MIPS peak, 32-bit microprocessor with on-chip cache
M Horowitz, P Chow, D Stark, RT Simoni, A Salz, S Przybylski, ...
IEEE Journal of Solid-State Circuits 22 (5), 790-799, 1987
1131987
The Transmogrifier-2: A 1 million gate rapid prototyping system
DM Lewis, DR Galloway, M van Ierssel, J Rose, P Chow
Proceedings of the 1997 ACM fifth international symposium on Field …, 1997
1111997
Enabling flexible network FPGA clusters in a heterogeneous cloud data center
N Tarafdar, T Lin, E Fukuda, H Bannazadeh, A Leon-Garcia, P Chow
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
1102017
How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors?
KI Farkas, NP Jouppi, P Chow
Proceedings of 1995 1st IEEE Symposium on High Performance Computer …, 1995
1011995
Architectural Tradeoffs in the Design of MIPS-X
P Chow, M Horowitz
Proceedings of the 14th Annual International Symposium on Computer …, 1987
971987
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