| Fpga-based face detection system using haar classifiers J Cho, S Mirzaei, J Oberg, R Kastner Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2009 | 240 | 2009 |
| SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip HMG Wassel, Y Gao, JK Oberg, T Huffmire, R Kastner, FT Chong, ... ACM SIGARCH Computer Architecture News 41 (3), 583-594, 2013 | 167 | 2013 |
| Sapper: A language for hardware-level security policy enforcement X Li, V Kashyap, JK Oberg, M Tiwari, VR Rajarathinam, R Kastner, ... Proceedings of the 19th international conference on Architectural support …, 2014 | 161 | 2014 |
| Caisson: a hardware description language for secure information flow X Li, M Tiwari, JK Oberg, V Kashyap, FT Chong, T Sherwood, ... ACM Sigplan Notices 46 (6), 109-120, 2011 | 158 | 2011 |
| Accelerating Viola-Jones face detection to FPGA-level using GPUs D Hefenbrock, J Oberg, NTN Thanh, R Kastner, SB Baden 2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010 | 157 | 2010 |
| Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security M Tiwari, JK Oberg, X Li, J Valamehr, T Levin, B Hardekopf, R Kastner, ... ACM SIGARCH Computer Architecture News 39 (3), 189-200, 2011 | 147 | 2011 |
| Detecting hardware trojans with gate-level information-flow tracking W Hu, B Mao, J Oberg, R Kastner Computer 49 (8), 44-52, 2016 | 101 | 2016 |
| Information flow isolation in I2C and USB J Oberg, W Hu, A Irturk, M Tiwari, T Sherwood, R Kastner Proceedings of the 48th Design Automation Conference, 254-259, 2011 | 79 | 2011 |
| Theoretical fundamentals of gate level information flow tracking W Hu, J Oberg, A Irturk, M Tiwari, T Sherwood, D Mu, R Kastner IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 74 | 2011 |
| Leveraging gate-level properties to identify hardware timing channels J Oberg, S Meiklejohn, T Sherwood, R Kastner IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 56 | 2014 |
| On the complexity of generating gate level information flow tracking logic W Hu, J Oberg, A Irturk, M Tiwari, T Sherwood, D Mu, R Kastner IEEE Transactions on Information Forensics and Security 7 (3), 1067-1080, 2012 | 52 | 2012 |
| Random Decision Tree Body Part Recognition Using FPGAs J Oberg, K Eguro, R Bittner, A Forin Field Programmable Logic and Applications (FPL), 2012 22nd International …, 2012 | 48 | 2012 |
| Minimal multi-threading: Finding and removing redundant instructions in multi-threaded processors G Long, D Franklin, S Biswas, P Ortiz, J Oberg, D Fan, FT Chong 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 337-348, 2010 | 44 | 2010 |
| Theoretical analysis of gate level information flow tracking J Oberg, W Hu, A Irturk, M Tiwari, T Sherwood, R Kastner Proceedings of the 47th Design Automation Conference, 244-247, 2010 | 43 | 2010 |
| Gate-level information flow tracking for security lattices W Hu, D Mu, J Oberg, B Mao, M Tiwari, T Sherwood, R Kastner ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (1 …, 2014 | 42 | 2014 |
| Networks on chip with provable security properties HMG Wassel, Y Gao, JK Oberg, T Huffmire, R Kastner, FT Chong, ... IEEE Micro 34 (3), 57-68, 2014 | 42 | 2014 |
| Decision tree computation in hardware utilizing a physically distinct integrated circuit with on-chip memory and a reordering of data to be grouped J Oberg, K Eguro, V Tirva, P Parthasarathy, S Carrie, A Forin, J Chow US Patent 9,292,767, 2016 | 25 | 2016 |
| A software-based dynamic-warp scheduling approach for load-balancing the Viola–Jones face detection algorithm on GPUs T Nguyen, D Hefenbrock, J Oberg, R Kastner, S Baden Journal of Parallel and Distributed Computing 73 (5), 677-685, 2013 | 23 | 2013 |
| Expanding gate level information flow tracking for multilevel security W Hu, J Oberg, J Barrientos, D Mu, R Kastner IEEE Embedded Systems Letters 5 (2), 25-28, 2013 | 22 | 2013 |
| Eliminating timing information flows in a mix-trusted system-on-chip J Oberg, T Sherwood, R Kastner IEEE Design & Test 30 (2), 55-62, 2013 | 22 | 2013 |
Ryan KastnerProfessor of Computer Science and Engineering, UCSD在 ucsd.edu 的電子郵件地址已通過驗證
