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Salvador Petit
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Multi2sim: A simulation framework to evaluate multicore-multithreaded processors
R Ubal, J Sahuquillo, S Petit, P Lopez
19th International Symposium on Computer Architecture and High Performance …, 2007
2492007
A simple power-aware scheduling for multicore systems when running real-time applications
D Bautista, J Sahuquillo, H Hassan, S Petit, J Duato
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-7, 2008
842008
Exploiting temporal locality in drowsy cache policies
S Petit, J Sahuquillo, JM Such, D Kaeli
Proceedings of the 2nd conference on Computing frontiers, 371-377, 2005
732005
Application clustering policies to address system fairness with intel’s cache allocation technology
V Selfa, J Sahuquillo, L Eeckhout, S Petit, ME Gómez
2017 26th international conference on parallel architectures and compilation …, 2017
642017
An hybrid eDRAM/SRAM macrocell to implement first-level data caches
A Valero, J Sahuquillo, S Petit, V Lorente, R Canal, P López, J Duato
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
472009
L1-bandwidth aware thread allocation in multicore SMT processors
J Feliu, J Sahuquillo, S Petit, J Duato
Proceedings of the 22nd international conference on Parallel architectures …, 2013
402013
Perf&Fair: A progress-aware scheduler to enhance performance and fairness in SMT multicores
J Feliu, J Sahuquillo, S Petit, J Duato
IEEE Transactions on Computers 66 (5), 905-911, 2016
352016
Addressing fairness in SMT multicores with a progress-aware scheduler
J Feliu, J Sahuquillo, S Petit, J Duato
2015 ieee international parallel and distributed processing symposium, 187-196, 2015
332015
Cache-hierarchy contention-aware scheduling in CMPs
J Feliu, S Petit, J Sahuquillo, J Duato
IEEE Transactions on Parallel and Distributed Systems 25 (3), 581-590, 2013
332013
Power‐aware scheduling with effective task migration for real‐time multicore embedded systems
JL March, J Sahuquillo, S Petit, H Hassan, J Duato
Concurrency and Computation: Practice and Experience 25 (14), 1987-2001, 2013
312013
A complexity-effective out-of-order retirement microarchitecture
SP Marti, JS Borras, PL Rodriguez, RU Tena, JD Marin
IEEE Transactions on computers 58 (12), 1626-1639, 2009
292009
Understanding cache hierarchy contention in CMPs to improve job scheduling
J Feliu, J Sahuquillo, S Petit, J Duato
2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012
242012
Design of hybrid second-level caches
A Valero, J Sahuquillo, S Petit, P López, J Duato
IEEE Transactions on Computers 64 (7), 1884-1897, 2014
232014
A new energy-aware dynamic task set partitioning algorithm for soft and hard embedded real-time systems
JL March, J Sahuquillo, H Hassan, S Petit, J Duato
The Computer Journal 54 (8), 1282-1294, 2011
222011
Symbiotic job scheduling on the IBM POWER8
J Feliu, S Eyerman, J Sahuquillo, S Petit
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
212016
Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches
A Valero, S Petit, J Sahuquillo, P López, J Duato
IEEE Transactions on Computers 61 (9), 1231-1242, 2011
212011
On microarchitectural mechanisms for cache wearout reduction
A Valero, N Miralaei, S Petit, J Sahuquillo, TM Jones
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3), 857-871, 2016
202016
Bandwidth-aware on-line scheduling in SMT multicores
J Feliu, J Sahuquillo, S Petit, J Duato
IEEE Transactions on Computers 65 (2), 422-434, 2015
202015
Phase-aware cache partitioning to target both turnaround time and system performance
L Pons, J Sahuquillo, V Selfa, S Petit, J Pons
IEEE Transactions on Parallel and Distributed Systems 31 (11), 2556-2568, 2020
182020
Spim-cache: A pedagogical tool for teaching cache memories through code-based exercises
J Sahuquillo, N Tomás, S Petit, A Pont
IEEE Transactions on Education 50 (3), 244-250, 2007
162007
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Articles 1–20