| Power and area efficient approximate heterogeneous 8T SRAM for multimedia applications PK Bharti, N Surana, J Mekie 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 5 | 2019 |
| Compute-in-memory using 6T SRAM for a wide variety of workloads PK Bharti, S Jain, KR Pillai, SV Sayyaparaju, GS Kalsi, J Mekie, ... 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2963-2967, 2022 | 3 | 2022 |
| Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H. 264 video decoder PK Bharti, N Surana, J Mekie IET Computers & Digital Techniques 13 (6), 505-513, 2019 | 2 | 2019 |
| Gbrhq-14t: Gate-boosted radiation hardened quadruple sram design PK Bharti, J Mekie 2022 IEEE International Conference on Emerging Electronics (ICEE), 1-5, 2022 | 1 | 2022 |
| Abdulazeez, Falah Amer, 271 S Abhishek, J Agarwal, A Agrawal, S Agrawal, N Ahmad, D Ajabani, ... | | 2023 |
| RHSCC-16T: radiation hardened sextuple cross coupled robust SRAM design for radiation prone environments PK Bharti, J Mekie 2022 IEEE 40th International Conference on Computer Design (ICCD), 17-24, 2022 | | 2022 |
| RTQCC-14T: radiation tolerant quadruple cross coupled robust SRAM design for radiation prone environments PK Bharti, J Mekie International Symposium on VLSI Design and Test, 486-498, 2022 | | 2022 |
| Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks N Surana, PK Bharti, BV Tej, J Mekie 2022 35th International Conference on VLSI Design and 2022 21st …, 2022 | | 2022 |
| 2022 IEEE 40th International Conference on Computer Design (ICCD)| 978-1-6654-6186-3/22/$31.00© 2022 IEEE| DOI: 10.1109/ICCD56317. 2022.00118 J Abella, D Abraham, T Adegbija, M Alam, L Albarakat, U Ali, H Ando, ... | | |
| 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID)| 978-1-6654-8505-0/22/$31.00© 2022 IEEE| DOI: 10.1109 … Z Abbas, A Agrawal, K Agrawal, M Alam, A Alaql, A Ali, P Aristodemou, ... | | |
| 16.64 Gbps Synchronous CML SerDes Transceiver Design Technique with Process Corner Variations for Low Power Application MS Choudhary, M Kumawat, PK Bharti, SK Vishvakarma | | |
