| 4.5 a 9.25 GHz digital PLL with fractional-spur cancellation based on a multi-DTC topology G Castoro, SM Dartizio, F Tesolin, F Buccoleri, M Rossoni, D Cherniak, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 82-84, 2023 | 8 | 2023 |
| 4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering SM Dartizio, F Tesolin, G Castoro, F Buccoleri, L Lanzoni, M Rossoni, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 3-5, 2023 | 8 | 2023 |
| A Low-Spur and Low-Jitter Fractional- Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering SM Dartizio, F Tesolin, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ... IEEE Journal of Solid-State Circuits, 2023 | 2 | 2023 |
| Phase noise analysis of periodically ON/OFF switched oscillators G Castoro, SM Dartizio, AL Lacaita, S Levantino IEEE Transactions on Circuits and Systems I: Regular Papers 70 (1), 54-63, 2022 | 2 | 2022 |
| 10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion F Tesolin, SM Dartizio, G Castoro, F Buccoleri, M Rossoni, D Cherniak, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 198-200, 2024 | | 2024 |
| 10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM M Rossoni, SM Dartizio, F Tesolin, G Castoro, R Dell’Orto, C Samori, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 188-190, 2024 | | 2024 |
| Progetto di un moltiplicatore di frequenza power-gated in tecnologia CMOS 28nm per applicazioni ad onde millimetriche G Castoro | | 2019 |
Simone DartizioPolitecnico di MilanoVerified email at mail.polimi.it
