| Novel high speed vedic multiplier proposal incorporating adder based on quaternary signed digit number system P Dalmia, A Parashar, A Tomar, N Pandey 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 7 | 2018 |
| Fast combinational architecture for a vedic divider A Parashar, G Aggarwal, R Dang, P Dalmia, N Pandey 2017 14th IEEE India Council International Conference (INDICON), 1-5, 2017 | 7 | 2017 |
| Only buffer when you need to: Reducing on-chip gpu traffic with reconfigurable local atomic buffers P Dalmia, R Mahapatra, MD Sinclair 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 4 | 2022 |
| Hardware/software co-design of a high-speed Othello solver P Gangwar, S Maurya, S Garg, S Goyal, AS Kumar, P Dalmia, N Pandey 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems …, 2019 | 4 | 2019 |
| An FPGA based floating point Gauss-Seidel iterative solver R Joshi, A Raghuvanshi, Y Gilhotra, S Sharma, S Sharma, P Dalmia, ... 2017 14th IEEE India Council International Conference (INDICON), 1-6, 2017 | 3 | 2017 |
| Improving the Scalability of GPU Synchronization Primitives P Dalmia, R Mahapatra, J Intan, D Negrut, MD Sinclair IEEE Transactions on Parallel and Distributed Systems 34 (1), 275-290, 2022 | 2 | 2022 |
| Reducing Synchronization and Communication Overheads in GPUs P Dalmia The University of Wisconsin-Madison, 2023 | | 2023 |
ROHAN MAHAPATRAUniversity of California San DiegoVerified email at ucsd.edu
