| 15.2 A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and ping-pong CIM with simultaneous computation and weight updating J Yue, X Feng, Y He, Y Huang, Y Wang, Z Yuan, M Zhan, J Liu, JW Su, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 238-240, 2021 | 114 | 2021 |
| A second-order noise-shaping SAR ADC with passive integrator and tri-level voting H Zhuang, W Guo, J Liu, H Tang, Z Zhu, L Chen, N Sun IEEE Journal of Solid-State Circuits 54 (6), 1636-1647, 2019 | 94 | 2019 |
| Energy‐efficient hybrid capacitor switching scheme for SAR ADC L Xie, G Wen, J Liu, Y Wang Electronics Letters 50 (1), 22-23, 2014 | 87 | 2014 |
| A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, S Li, ... IEEE Journal of Solid-State Circuits 55 (12), 3248-3259, 2020 | 68 | 2020 |
| A 0.029-mm 2 17-fJ/Conversion-Step Third-Order CT ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer J Liu, S Li, W Guo, G Wen, N Sun IEEE Journal of Solid-State Circuits 54 (2), 428-440, 2019 | 62 | 2019 |
| 9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping J Liu, X Wang, Z Gao, M Zhan, X Tang, N Sun 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 158-160, 2020 | 60 | 2020 |
| 27.4 A 0.4-to-40MS/s 75.7 dB-SNDR fully dynamic event-driven pipelined ADC with 3-stage cascoded floating inverter amplifier X Tang, X Yang, J Liu, W Shi, DZ Pan, N Sun 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 376-378, 2021 | 47 | 2021 |
| A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation J Liu, X Tang, W Zhao, L Shen, N Sun IEEE Journal of Solid-State Circuits 55 (12), 3260-3270, 2020 | 45 | 2020 |
| 9.5 a 13.5 b-ENOB second-order noise-shaping SAR with PVT-robust closed-loop dynamic amplifier X Tang, X Yang, W Zhao, CK Hsu, J Liu, L Shen, A Mukherjee, W Shi, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 162-164, 2020 | 42 | 2020 |
| Low-power SAR ADC design: Overview and survey of state-of-the-art techniques X Tang, J Liu, Y Shen, S Li, L Shen, A Sanyal, K Ragab, N Sun IEEE Transactions on Circuits and Systems I: Regular Papers 69 (6), 2249-2262, 2022 | 37 | 2022 |
| 27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering J Liu, D Li, Y Zhong, X Tang, N Sun 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 369-371, 2021 | 35 | 2021 |
| 18.2 a 16fJ/Conversion-step time-domain two-step Capacitance-to-Digital converter X Tang, S Li, L Shen, W Zhao, X Yang, R Williams, J Liu, Z Tan, N Hall, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 296-297, 2019 | 31 | 2019 |
| Energy‐efficient capacitor‐splitting DAC scheme with high accuracy for SAR ADCs L Xie, J Su, J Liu, G Wen Electronics Letters 51 (6), 460-462, 2015 | 29 | 2015 |
| 16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation J Liu, X Tang, W Zhao, L Shen, N Sun 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2020 | 28 | 2020 |
| A fully dynamic low-power wideband time-interleaved noise-shaping SAR ADC H Zhuang, J Liu, H Tang, X Peng, N Sun IEEE Journal of Solid-State Circuits 56 (9), 2680-2690, 2021 | 27 | 2021 |
| Error-feedback mismatch error shaping for high-resolution data converters J Liu, CK Hsu, X Tang, S Li, G Wen, N Sun IEEE Transactions on Circuits and Systems I: Regular Papers 66 (4), 1342-1354, 2019 | 26 | 2019 |
| A 0.029MM2 17-FJ/Conv.-Step CT ADC with 2nd-Order Noise-Shaping SAR Quantizer J Liu, S Li, W Guo, G Wen, N Sun 2018 IEEE symposium on VLSI circuits, 201-202, 2018 | 26 | 2018 |
| A 7-bit 900-MS/s 2-then-3-bit/cycle SAR ADC with background offset calibration D Li, Z Zhu, J Liu, H Zhuang, Y Yang, N Sun IEEE Journal of Solid-State Circuits 55 (11), 3051-3063, 2020 | 25 | 2020 |
| A 90-dB-SNDR calibration-free fully passive noise-shaping SAR ADC with 4× passive gain and second-order DAC mismatch error shaping J Liu, X Wang, Z Gao, M Zhan, X Tang, CK Hsu, N Sun IEEE Journal of Solid-State Circuits 56 (11), 3412-3423, 2021 | 23 | 2021 |
| An energy-efficient time-domain incremental zoom capacitance-to-digital converter X Tang, S Li, X Yang, L Shen, W Zhao, RP Williams, J Liu, Z Tan, NA Hall, ... IEEE Journal of Solid-State Circuits 55 (11), 3064-3075, 2020 | 21 | 2020 |
Nan Sun (孙楠)Tsinghua UniversityVerified email at tsinghua.edu.cn
