| Method and system for forming a layer with controllable spstial variation C Wajda, D O'Meara, M Igeta US Patent App. 11/231,335, 2007 | 462 | 2007 |
| Memory device that includes passivated nanoclusters and method for manufacture R Muralidhar, CK Subramanian, S Madhukar, BE White, MA Sadd, S Zafar, ... US Patent 6,297,095, 2001 | 179 | 2001 |
| Perspective: New process technologies required for future devices and scaling R Clark, K Tapily, KH Yu, T Hakamata, S Consiglio, D O’meara, C Wajda, ... Apl Materials 6 (5), 2018 | 175 | 2018 |
| Process for forming a semiconductor device PJ Tobin, RI Hegde, HH Tseng, D O'meara, V Wang US Patent 5,972,804, 1999 | 142 | 1999 |
| Memory cell and method for programming thereof R Muralidhar, S Madhukar, B Jiang, BE White, SB Samavedam, ... US Patent 6,320,784, 2001 | 115 | 2001 |
| Method for forming a semiconductor device with an opening in a dielectric layer BY Nguyen, WJ Taylor Jr, PJ Tobin, DL O'meara, PV Gilbert, YJT Lii, ... US Patent 6,362,071, 2002 | 110 | 2002 |
| Deposition of silicon dioxide and silicon oxynitride films using azidosilane sources AK Hochberg, DL O'meara, DA Roberts US Patent 4,992,306, 1991 | 96 | 1991 |
| Memory device and method for manufacture S Madhukar, R Muralidhar, DL O'meara, KC Smith, BY Nguyen US Patent 6,344,403, 2002 | 94 | 2002 |
| Deposition of silicon oxide films using alkylsilane liquid sources AK Hochberg, DL O'meara US Patent 4,981,724, 1991 | 61 | 1991 |
| Multi-layer pattern for alternate ALD processes DL O'meara, A Mosden US Patent 8,809,169, 2014 | 51 | 2014 |
| PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology B Maiti, PJ Tobin, C Hobbs, RI Hegde, F Huang, DL O'Meara, D Jovanovic, ... International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 43 | 1998 |
| Process for forming a semiconductor device PJ Tobin, RI Hegde, HH Tseng, D O'meara, V Wang US Patent 6,297,173, 2001 | 41 | 2001 |
| Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications A Raley, S Thibaut, N Mohanty, K Subhadeep, S Nakamura, A Ko, ... Advanced Etch Technology for Nanopatterning V 9782, 30-43, 2016 | 35 | 2016 |
| The LPCVD of silicon oxide films below 400 C from liquid sources AK Hochberg, DL O'Meara J. Electrochem. Soc 136 (6), 1843-1844, 1989 | 35 | 1989 |
| Wafer heater assembly D O'Meara, G Leusink, S Cabral, A Dip, C Wajda, R Joe US Patent App. 10/813,119, 2005 | 32 | 2005 |
| Deposition of silicon nitride films from azidosilane sources AK Hochberg, DL O'meara, DA Roberts US Patent 4,992,299, 1991 | 31 | 1991 |
| Comparison of B2O3 and BN deposited by atomic layer deposition for forming ultrashallow dopant regions by solid state diffusion S Consiglio, RD Clark, D O'Meara, CS Wajda, K Tapily, GJ Leusink Journal of Vacuum Science & Technology A 34 (1), 2016 | 28 | 2016 |
| Multilayer sidewall spacer for seam protection of a patterned structure DL O'meara, A Dip, A Mosden, PH Chou, RA Conti US Patent 8,673,725, 2014 | 28 | 2014 |
| Spacer material modification to improve K-value and etch properties AD Raley, DL O'meara US Patent 9,171,736, 2015 | 27 | 2015 |
| Material processing to achieve sub-10nm patterning DL O'meara, AD Raley, A Ko, K Ito US Patent 9,443,731, 2016 | 26 | 2016 |
