| Managing cache coherency in a data processing apparatus E Özer, SD Biles, SA Ford US Patent 7,937,535, 2011 | 453 | 2011 |
| The ARM scalable vector extension N Stephens, S Biles, M Boettcher, J Eapen, M Eyole, G Gabrielli, ... IEEE micro 37 (2), 26-39, 2017 | 381 | 2017 |
| Handling access requests in a data processing apparatus DH Mansell, SD Biles, SJ Hill US Patent 7,657,694, 2010 | 256 | 2010 |
| An architecture framework for transparent instruction set customization in embedded processors N Clark, J Blome, M Chu, S Mahlke, S Biles, K Flautner 32nd International Symposium on Computer Architecture (ISCA'05), 272-283, 2005 | 211 | 2005 |
| Cache management within a data processing apparatus SD Biles, RR Grisenthwaite, DH Mansell US Patent 8,041,897, 2011 | 84 | 2011 |
| Cache miss detection in a data processing apparatus M Ghosh, E Özer, SD Biles US Patent 8,099,556, 2012 | 83 | 2012 |
| Contention management for a hardware transactional memory G Blake, TN Mudge, SD Biles, NYS Chong, E Ozer, RG Dreslinski US Patent App. 12/292,565, 2009 | 82 | 2009 |
| Contention management for a hardware transactional memory SD Biles, G Blake, TN Mudge US Patent 9,513,959, 2016 | 79 | 2016 |
| Multiple thread instruction fetch from different cache levels E Özer, SD Biles US Patent 7,769,955, 2010 | 77 | 2010 |
| Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion JFM Pruvost, NBE Lataille, SD Biles US Patent 7,162,590, 2007 | 66 | 2007 |
| Data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuirty DH Mansell, RR Grisenthwaite, SD Biles US Patent 8,418,175, 2013 | 63 | 2013 |
| Efficiency of cache memory operations SD Biles, NC Paver, C Sudanthi, TC Mace US Patent 8,001,331, 2011 | 58 | 2011 |
| Handling of write access requests to shared memory in a data processing apparatus FCM Piry, PJ Raphalen, NBE Lataille, SD Biles, RR Grisenthwaite US Patent 8,271,730, 2012 | 56 | 2012 |
| Apparatus and method for loading data values SD Biles, CB Dornan, V Vasekin, AC Rose US Patent 7,111,126, 2006 | 54 | 2006 |
| Reuseable configuration data SD Biles, K Flautner, S Mahlke, N Clark US Patent 7,318,143, 2008 | 51 | 2008 |
| Program subgraph identification SD Biles, K Flautner, S Mahlke, N Clark US Patent 7,343,482, 2008 | 50 | 2008 |
| Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches M Ghosh, E Ozer, S Ford, S Biles, HHS Lee Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009 | 49 | 2009 |
| Memory domain based security control with data processing systems D Kershaw, SD Biles, RR Grisenthwaite US Patent 7,966,466, 2011 | 46 | 2011 |
| Instruction issue control within a multi-threaded in-order superscalar processor E Özer, V Vasekin, SD Biles US Patent 7,707,390, 2010 | 40 | 2010 |
| Data processing apparatus and method for handling corrupted data values SD Biles US Patent 7,269,759, 2007 | 39 | 2007 |
