| Haswell: The fourth-generation intel core processor P Hammarlund, AJ Martinez, AA Bajwa, DL Hill, E Hallnor, H Jiang, ... IEEE micro 34 (2), 6-20, 2014 | 362 | 2014 |
| Controlling time stamp counter (TSC) offsets for mulitple cores and threads MG Dixon, JJ Shrall, RS Parthasarathy US Patent 8,700,943, 2014 | 219 | 2014 |
| Transactional memory in out-of-order processors with XABORT having immediate argument R Rajwar, MG Dixon, KK Lai US Patent 8,301,849, 2012 | 115 | 2012 |
| Method, apparatus, and system for speculative execution event counter checkpointing and restoring LA Knauth, R Rajwar, PJ Irelan, MG Dixon, KK Lai US Patent App. 13/365,104, 2012 | 102 | 2012 |
| Breakthrough AES performance with intel AES new instructions K Akdemir, M Dixon, W Feghali, P Fay, V Gopal, J Guilford, E Ozturk, ... White paper, June 12, 217, 2010 | 90 | 2010 |
| Flexible architecture and instruction for advanced encryption standard (AES) S Gueron, WK Feghali, V Gopal, M Raghunandan, MG Dixon, ... US Patent 8,538,015, 2013 | 88 | 2013 |
| Gathering and scattering multiple data elements CJ Hughes, YKYK Chen, M Bomb, JW Brandt, MJ Buxton, MJ Charney, ... US Patent 8,447,962, 2013 | 82 | 2013 |
| 8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package W Gomes, S Khushu, DB Ingerly, PN Stover, NI Chowdhury, F O'Mahony, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 144-146, 2020 | 71 | 2020 |
| SIMD integer multiply-accumulate instruction for multi-precision arithmetic V Gopal, GM Wolrich, E Ozturk, JD Guilford, KS Yap, SM Gulley, ... US Patent 9,235,414, 2016 | 58 | 2016 |
| 4th generation Intel core processor, codenamed haswell P Hammarlund, AJ Martinez, A Bajwa, DL Hill, E Hallnor, H Jiang, ... Hot chips 25, 2013 | 52 | 2013 |
| Method, apparatus, and system for speculative abort control mechanisms MG Dixon, R Rajwar, KK Lai, RS Chappell, RS Parthasarathy, AJ Farcy, ... US Patent App. 13/997,248, 2014 | 45 | 2014 |
| Performing AES encryption or decryption in multiple modes with a single instruction M Dixon, S Chennupaty, S Gueron US Patent 8,538,012, 2013 | 45 | 2013 |
| Intel transactional synchronization extensions R Rajwar, M Dixon Intel Developer Forum San Francisco 2012, 2012 | 44 | 2012 |
| Digital random number generator using partially entropic data HC Herbert, GW Cox, S Gueron, J Walker, CE Dike, SA Fischer, E Brickell, ... US Patent 8,489,660, 2013 | 43 | 2013 |
| Matrix multiply accumulate instruction V Gopal, GM Wolrich, KS Yap, JD Guilford, E Ozturk, SM Gulley, ... US Patent 9,960,917, 2018 | 38 | 2018 |
| Managing and implementing metadata in central processing unit using register extensions BV Patel, R Gopalakrishna, AF Glew, RJ Kushlis, DA Van Dyke, JF Cihula, ... US Patent 8,635,415, 2014 | 37 | 2014 |
| Method and apparatus to process SHA-2 secure hashing algorithm KS Yap, GM Wolrich, JD Guilford, V Gopal, E Ozturk, SM Gulley, ... US Patent 9,632,782, 2017 | 34 | 2017 |
| Instruction for enabling a processor wait state MG Dixon, SD Rodgers, T Bahrami, SH Gunther, P Sethi, P Hammarlund US Patent 8,464,035, 2013 | 34 | 2013 |
| QoS based binary translation and application streaming B Muthiah, WB Rash, G Hinton, MG Dixon, S Hayn, D Papworth US Patent 9,525,586, 2016 | 32 | 2016 |
| Method, apparatus, and system for transactional speculation control instructions R Rajwar, MG Dixon, KK Lai, AJ Farcy, BL Toll, RS Chappell, MC Merten, ... US Patent App. 13/997,243, 2015 | 32 | 2015 |
