| A 7.6 mW, 414 fs RMS-jitter 10 GHz phase-locked loop for a 40 Gb/s serial link transmitter based on a two-stage ring oscillator in 65 nm CMOS W Bae, H Ju, K Park, SY Cho, DK Jeong IEEE Journal of Solid-State Circuits 51 (10), 2357-2367, 2016 | 75 | 2016 |
| A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference J Lee, K Lee, H Kim, B Kim, K Park, DK Jeong IEEE Journal of Solid-State Circuits 55 (8), 2186-2195, 2020 | 46 | 2020 |
| A 6.7–11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS K Park, W Bae, J Lee, J Hwang, DK Jeong IEEE Journal of Solid-State Circuits 53 (10), 2982-2993, 2018 | 37 | 2018 |
| A 0.36 pJ/bit, 0.025 mm, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 63 (9), 1393-1403, 2016 | 29 | 2016 |
| A 4–20-Gb/s 1.87-pJ/b continuous-rate digital CDR circuit with unlimited frequency acquisition capability in 65-nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong IEEE Journal of Solid-State Circuits 56 (5), 1597-1607, 2020 | 28 | 2020 |
| 8 An output-bandwidth-optimized 200Gb/s PAM-4 100Gb/s NRZ transmitter with 5-Tap FFE in 28nm CMOS M Choi, Z Wang, K Lee, K Park, Z Liu, A Biswas, J Han, E Alon 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 128-130, 2021 | 27 | 2021 |
| 6.5 A 6.4-to-32Gb/s 0.96 pJ/b referenceless CDR employing ML-inspired stochastic phase-frequency detection technique in 40nm CMOS K Park, M Shim, HG Ko, DK Jeong 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 124-126, 2020 | 27 | 2020 |
| An output bandwidth optimized 200-Gb/s PAM-4 100-Gb/s NRZ transmitter with 5-tap FFE in 28-nm CMOS Z Wang, M Choi, K Lee, K Park, Z Liu, A Biswas, J Han, S Du, E Alon IEEE Journal of Solid-State Circuits 57 (1), 21-31, 2021 | 22 | 2021 |
| A 2.44-pJ/b 1.62–10-Gb/s receiver for next generation video interface equalizing 23-dB loss with adaptive 2-tap data DFE and 1-tap edge DFE J Lee, K Park, K Lee, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 65 (10), 1295-1299, 2018 | 20 | 2018 |
| 6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels HG Ko, S Shin, J Oh, K Park, DK Jeong 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 128-130, 2020 | 19 | 2020 |
| A 64Gb/s 2.29 pJ/b PAM-4 VCSEL transmitter with 3-tap asymmetric FFE in 65nm CMOS J Hwang, HS Choi, H Do, GS Jeong, D Koh, K Park, S Kim, DK Jeong 2019 Symposium on VLSI Circuits, C268-C269, 2019 | 18 | 2019 |
| A supply-scalable-serializing transmitter with controllable output swing and equalization for next-generation standards W Bae, H Ju, K Park, J Han, DK Jeong IEEE Transactions on Industrial Electronics 65 (7), 5979-5989, 2017 | 15 | 2017 |
| A 0.1 pJ/b/dB 1.62-to-10.8 Gb/s video interface receiver with fully adaptive equalization using un-even data level J Lee, K Lee, H Kim, B Kim, K Park, DK Jeong 2019 Symposium on VLSI Circuits, C198-C199, 2019 | 12 | 2019 |
| Design techniques for a 6.4–32-Gb/s 0.96-pJ/b continuous-rate CDR with stochastic frequency–phase detector K Park, M Shim, HG Ko, B Nikolić, DK Jeong IEEE Journal of Solid-State Circuits 57 (2), 573-585, 2021 | 11 | 2021 |
| A 15-GHz, 17.8-mW, 213-fs injection-locked PLL with maximized injection strength using adjustment of phase domain response MS Choo, Y Song, SY Cho, HG Ko, K Park, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 66 (12), 1932-1936, 2019 | 9 | 2019 |
| A 4-to-20Gb/s 1.87 pJ/b referenceless digital CDR with unlimited frequency detection capability in 65nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong 2019 Symposium on VLSI Circuits, C194-C195, 2019 | 9 | 2019 |
| A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control K Park, W Bae, DK Jeong 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 9 | 2017 |
| A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS K Park, W Bae, H Ju, J Lee, GS Jeong, Y Kim, DK Jeong 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2389-2392, 2015 | 9 | 2015 |
| A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 447-450, 2014 | 9 | 2014 |
| An adaptive offset cancellation scheme and shared-summer adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s low-power receiver in 40 nm CMOS K Lee, H Kim, W Jung, J Lee, H Ju, K Park, O Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 68 (2), 622-626, 2020 | 8 | 2020 |
Deog-Kyoon JeongSeoul National University, Department of Electrical and Computer Engineering在 snu.ac.kr 的电子邮件经过验证
