| Ambient temperature-induced device self-heating effects on multi-fin Si n-FinFET performance S Venkateswarlu, A Sudarsanan, SG Singh, K Nayak IEEE Transactions on Electron Devices 65 (7), 2721-2728, 2018 | 43 | 2018 |
| Impact of fin line edge roughness and metal gate granularity on variability of 10-nm node SOI n-FinFET A Sudarsanan, S Venkateswarlu, K Nayak IEEE Transactions on Electron Devices 66 (11), 4646-4652, 2019 | 28 | 2019 |
| Superior work function variability performance of horizontally stacked nanosheet FETs for sub-7-nm technology and beyond A Sudarsanan, S Venkateswarlu, K Nayak 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020 | 12 | 2020 |
| Immunity to random fluctuations induced by interface trap variability in Si gate-all-around n-nanowire field-effect transistor devices A Sudarsanan, K Nayak Journal of Computational Electronics 20 (3), 1169-1177, 2021 | 5 | 2021 |
| TCAD-based investigation of statistical variability immunity in U-channel FDSOI n-MOSFET for sub-7-nm technology A Sudarsanan, K Nayak IEEE Transactions on Electron Devices 68 (6), 2611-2617, 2021 | 4 | 2021 |
| Superior interface trap variability immunity of horizontally stacked Si nanosheet FET in Sub-3-nm technology node A Sudarsanan, O Badami, K Nayak 2021 International Semiconductor Conference (CAS), 161-164, 2021 | 2 | 2021 |
| Improved Electro-Thermal Performance in FinFETs using SOD Technology for 7nm node High Performance Logic Devices S Venkateswarlu, A Sudarsanan, K Nayak | | 2019 |
| Impact of Phonon Boundary Scattering on Self-heating Effects in Stacked Si Nano-sheet FET in sub-7nm Logic Technologies S Venkateswarlu, A Sudarsanan, K Nayak | | 2019 |
Venkateswarlu SankataliPh.D, R&D Engineer, IMEC, BelgiumVerified email at imec.be
