| Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks S Wang, D Zhou, X Han, T Yoshimura Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 71 | 2017 |
| CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks X Han, D Zhou, S Wang, S Kimura 2016 IEEE 34th International Conference on Computer Design (ICCD), 320-327, 2016 | 43 | 2016 |
| 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications D Zhou, S Wang, H Sun, J Zhou, J Zhu, Y Zhao, J Zhou, S Zhang, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 266-268, 2016 | 34 | 2016 |
| An 8K H. 265/HEVC video decoder chip with a new system pipeline design D Zhou, S Wang, H Sun, J Zhou, J Zhu, Y Zhao, J Zhou, S Zhang, ... IEEE Journal of Solid-State Circuits 52 (1), 113-126, 2016 | 25 | 2016 |
| VLSI Implementation of HEVC Motion Compensation with Distance Biased Direct Cache Mapping for 8K UHDTV Applications S Wang, D Zhou, J Zhou, T Yoshimura, S Goto IEEE, 2016 | 18 | 2016 |
| A dual-clock VLSI design of H. 265 sample adaptive offset estimation for 8k ultra-HD TV encoding J Zhou, D Zhou, S Wang, S Zhang, T Yoshimura, S Goto IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 714-724, 2016 | 16 | 2016 |
| Motion compensation architecture for 8K UHDTV HEVC decoder S Wang, D Zhou, S Goto 2014 IEEE International Conference on Multimedia and Expo (ICME), 1-6, 2014 | 14 | 2014 |
| Energy-efficient scheduling method with cross-loop model for resource-limited CNN accelerator designs K Yang, S Wang, J Zhou, T Yoshimura 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 7 | 2017 |
| High performance VLSI architecture of H. 265/HEVC intra prediction for 8K UHDTV video decoder J Zhou, D Zhou, S Wang, T Yoshimura, S Goto IEICE Transactions on Fundamentals of Electronics, Communications and …, 2015 | 6 | 2015 |
| Perceptual image compression using relativistic average least squares gans Z Cheng, T Fu, J Hu, L Guo, S Wang, X Zhao, D Zhou, Y Song Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2021 | 5 | 2021 |
| Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA Z Zhang, D Zhou, S Wang, S Kimura 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 184-189, 2018 | 5 | 2018 |
| Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder S Wang, D Zhou, J Zhou, T Yoshimura, S Goto Pacific Rim Conference on Multimedia, 74-83, 2014 | 2 | 2014 |
| Unified parameter decoder architecture for H.265/HEVC motion vector and boundary strength decoding S Wang, D Zhou, J Zhou, T Yoshimura, S Goto IEICE Transactions on Fundamentals of Electronics, Communications and …, 2015 | 1 | 2015 |
| Initial experience with right lobe living donor liver transplantation VH de Villa, CL Chen, YS Chen, CC Wang, SH Wang, S Goto, YC Chiang, ... Transplantation proceedings 32 (7), 2158-2159, 2000 | 1 | 2000 |
| D-11-69 Memory Organization in HEYC Motion Compensation For UHDTY Luma and Chroma Parallel W Shihao, Z Dajiang, G Satoshi 電子情報通信学会総合大会講演論文集 2014 (2), 69, 2014 | | 2014 |
Dajiang ZhouAnt Financial在 antfin.com 的电子邮件经过验证
