| An optimum loop gain tracking all-digital PLL using autocorrelation of bang–bang phase-frequency detection S Jang, S Kim, SH Chu, GS Jeong, Y Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 62 (9), 836-840, 2015 | 62 | 2015 |
| A 0.36 pJ/bit, 0.025 mm , 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 63 (9), 1393-1403, 2016 | 29 | 2016 |
| Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~ 1550 nm J Joo, KS Jang, SH Kim, IG Kim, JH Oh, SA Kim, GS Jeong, Y Kim, ... Optics express 23 (9), 12232-12243, 2015 | 26 | 2015 |
| A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection SY Cho, S Kim, MS Choo, J Lee, HG Ko, S Jang, SH Chu, W Bae, Y Kim, ... European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015-41st, 384-387, 2015 | 24 | 2015 |
| A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Bias GS Jeong, SH Chu, Y Kim, S Jang, S Kim, W Bae, SY Cho, H Ju, ... IEEE Journal of Solid-State Circuits 51 (10), 2312-2327, 2016 | 22 | 2016 |
| Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology W Bae, GS Jeong, Y Kim, HK Chi, DK Jeong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2016 | 20 | 2016 |
| An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation S Jang, S Kim, SH Chu, GS Jeong, Y Kim, DK Jeong VLSI Circuits (VLSI Circuits), 2015 Symposium on, C136-C137, 2015 | 19 | 2015 |
| A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm GS Jeong, SH Chu, Y Kim, S Jang, S Kim, W Bae, SY Cho, H Ju, ... Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian, 1-4, 2015 | 12 | 2015 |
| A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS K Park, W Bae, H Ju, J Lee, GS Jeong, Y Kim, DK Jeong Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 2389-2392, 2015 | 9 | 2015 |
| A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014-40th, 447-450, 2014 | 9 | 2014 |
| A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS Y Kim, W Bae, DK Jeong Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, 1869-1872, 2014 | 9 | 2014 |
| 20-Gb/s 5- and 25-Gb/s 3.8- Area-Efficient Modulator Drivers in 65-nm CMOS Y Kim, GS Jeong, JE Park, J Park, G Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 63 (11), 1034-1038, 2016 | 7 | 2016 |
| 20-Gb/s 3.6-V PP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS JE Park, Y Kim, S Kim, G Kim, DK Jeong Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 2864-2867, 2015 | 3 | 2015 |
| Test of the VCSEL driver based on Verilog-A VCSEL model J Hwang, GS Jeong, W Bae, Y Kim, G Kim, DK Jeong SoC Design Conference (ISOCC), 2015 International, 81-82, 2015 | 2 | 2015 |
| A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop S Kim, S Jang, JE Park, Y Kim, G Kim, DK Jeong Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 2856-2859, 2015 | 1 | 2015 |
