| Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures S Roy, MR Choudhury, R Puri, DZ Pan Design Automation Conference, 2013 | 49 | 2013 |
| Design for manufacturability and reliability in extreme-scaling VLSI B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan Science China Information Sciences 59, 1-23, 2016 | 45 | 2016 |
| Clock tree resynthesis for multi-corner multi-mode timing closure S Roy, PM Mattheakis, L Masse-Navette, DZ Pan Proceedings of the 2014 on International symposium on physical design, 69-76, 2014 | 45 | 2014 |
| Cross-layer optimization for high speed adders: A pareto driven machine learning approach Y Ma, S Roy, J Miao, J Chen, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 27 | 2018 |
| Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs S Roy, M Choudhury, R Puri, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 26 | 2015 |
| LRR-DPUF: Learning resilient and reliable digital physical unclonable function J Miao, M Li, S Roy, B Yu 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 21 | 2016 |
| OSFA: A new paradigm of aging aware gate-sizing for power/performance optimizations under multiple operating conditions S Roy, D Liu, J Singh, J Um, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 18 | 2016 |
| Triple patterning lithography layout decomposition using end-cutting B Yu, S Roy, JR Gao, DZ Pan Journal of Micro/Nanolithography, MEMS, and MOEMS 14 (1), 011002-011002, 2015 | 18 | 2015 |
| SD-PUF: Spliced digital physical unclonable function J Miao, M Li, S Roy, Y Ma, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 17 | 2017 |
| A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders S Roy, Y Ma, J Miao, B Yu 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 15 | 2017 |
| Reliability aware gate sizing combating NBTI and oxide breakdown S Roy, DZ Pan VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 …, 2014 | 15 | 2014 |
| High-speed adder design space exploration via graph neural processes H Geng, Y Ma, Q Xu, J Miao, S Roy, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 14 | 2021 |
| OSFA: A new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions S Roy, D Liu, J Um, DZ Pan Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 13 | 2015 |
| Evolving challenges and techniques for nanometer SoC clock network synthesis S Roy, PM Mattheakis, L Masse-Navette, DZ Pan Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE …, 2014 | 8 | 2014 |
| Automated synthesis of high-performance two operand binary parallel prefix adder M Choudhury, R Puri, S Roy, SC Sundararajan US Patent 8,527,920, 2013 | 8 | 2013 |
| Skew bounded buffer tree resynthesis for clock power optimization S Roy, DZ Pan, PM Mattheakis, PS Colyer, L Masse-Navette, PO Ribet Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 87-90, 2015 | 4 | 2015 |
| A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function S ROY, H Narayanan IEEE, 1991 | 4 | 1991 |
| Machine learning for statistical modeling: The case of perpendicular spin-transfer-torque random access memory U Roy, T Pramanik, S Roy, A Chatterjee, LF Register, SK Banerjee ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (3 …, 2021 | 3 | 2021 |
| CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction CH Lin, S Roy, CY Wang, DZ Pan, D Chen 2015 33rd IEEE International Conference on Computer Design (ICCD), 236-243, 2015 | 3 | 2015 |
| Large Scale VLSI Circuit Simulation Using Point Relaxation S Roy, Y Save, S Patkar, H Narayanan CSC, 2010 | 3 | 2010 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinVerified email at ece.utexas.edu
