Yuhwan Ro (노유환)
Yuhwan Ro (노유환)
Principal Researcher (Samsung Advanced Institute of Technology), Ph.D. (Seoul National University)
Verified email at - Homepage
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A 20nm 1.8 V 8Gb PRAM with 40MB/s program bandwidth
Y Choi, I Song, MH Park, H Chung, S Chang, B Cho, J Kim, Y Oh, D Kwon, ...
2012 IEEE International Solid-State Circuits Conference, 46-48, 2012
A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput
KJ Lee, BH Cho, WY Cho, S Kang, BG Choi, HR Oh, CS Lee, HJ Kim, ...
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical …, 2007
A 0.1- 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation
S Kang, WY Cho, BH Cho, KJ Lee, CS Lee, HR Oh, BG Choi, Q Wang, ...
IEEE Journal of Solid-State Circuits 42 (1), 210-218, 2006
Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations
YH Son, O Seongil, Y Ro, JW Lee, JH Ahn
Proceedings of the 40th Annual International Symposium on Computer …, 2013
A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2 TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications
YC Kwon, SH Lee, J Lee, SH Kwon, JM Ryu, JP Son, O Seongil, HS Yu, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 350-352, 2021
A 58nm 1.8 v 1gb pram with 6.4 mb/s program bw
H Chung, BH Jeong, BJ Min, Y Choi, BH Cho, J Shin, J Kim, J Sunwoo, ...
2011 IEEE International Solid-State Circuits Conference, 500-502, 2011
Variable resistance memory device and method of manufacturing the same
Y Ro, B Choi, W Cho, H Oh
US Patent 8,116,129, 2012
Resistance variable memory devices and read methods thereof
J Bae, D Kim, K Lee, H Oh, B Cho, B Choi, WY Cho, YH Ro
US Patent 8,243,542, 2012
A 0.1 μm 1.8 V 256Mb 66MHz synchronous burst PRAM
S Kang
ISSCC Digest of Technical Papers, Feb. 2006, 2006
Phase-changeable memory device and method of programming the same
H Kim, DE Kim, KJ Lee, YH Ro
US Patent 7,486,536, 2009
Phase change memory device and related programming method
YH Ro, KJ Lee, S Kang, WY Cho
US Patent 7,522,449, 2009
Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond
JH Kim, S Kang, S Lee, H Kim, W Song, Y Ro, S Lee, D Wang, H Shin, ...
2021 IEEE Hot Chips 33 Symposium (HCS), 1-26, 2021
Leveraging Power-performance Relationship of Energy-efficient Modern DRAM Devices
S Lee, H Cho, YH Son, Y Ro, NS Kim, JH Ahn
IEEE Access 6, 31387 - 31398, 2018
Non-volatile phase-change memory device and method of reading the same
YH Ro, WY Cho, BG Choi
US Patent 7,885,098, 2011
Phase-changeable memory device and read method thereof
WY Cho, BG Choi, DE Kim, HR Oh, BH Cho, YH Ro
US Patent 7,391,644, 2008
Phase change random access memory and method of testing the same
BG Choi, BH Cho, DE Kim, C Choi, YH Ro
US Patent 7,573,766, 2009
Aquabolt-XL HBM2-PIM, LPDDR5-PIM with in-memory processing, and AXDIMM with acceleration buffer
JH Kim, SH Kang, S Lee, H Kim, Y Ro, S Lee, D Wang, J Choi, J So, ...
IEEE Micro 42 (3), 20-30, 2022
Phase change memory devices and program methods
BG Choi, DE Kim, YH Ro, JY Choi, BH Cho, WY Cho
US Patent 7,499,316, 2009
Memory system including a resistance variable memory device
BG Choi, WY Cho, DE Kim, HR Oh, BH Cho, YH Ro
US Patent 7,668,007, 2010
Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems
Y Ro, M Sung, Y Park, JH Ahn
IEICE Electronics Express 14 (11), 2017
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