| Performance Study of GPU applications using SYCL and CUDA on Tesla V100 GPU GKR Kuncham, R Vaidya, M Barve IEEE High Performance Extreme Computing Conference (HPEC), 2021 | 17 | 2021 |
| Key-Value Store using High Level Synthesis Flow for Securities Trading System S Puranik, M Barve, D Shah, S Sinha, R Patrikar, S Rodi 2020 International Conference on Computing, Electronics & Communications …, 2020 | 5 | 2020 |
| Exactly-once transaction semantics for fault tolerant FPGA based transaction systems MK Nambiar, R Swapnil, SA Puranik, MD Barve US Patent 10,965,519, 2021 | 3 | 2021 |
| Workload Characterization in HPC Environment for Auto-scaling of Resources–Preliminary Study M Barve, S Sinha, RP Hardikar, A Gunturu, W Mallik 2022 IEEE 19th India Council International Conference (INDICON), 1-6, 2022 | 2 | 2022 |
| Synthesizing printf and scanf statements for generating debug messages in high-level synthesis (HLS) code MD Barve, SA Puranik, MK Nambiar, SS Rodi US Patent 11,714,742, 2023 | 1 | 2023 |
| FPGA-Based High-Throughput Key-Value Store Using Hashing and B-Tree for Securities Trading System S Puranik, M Barve, S Rodi, R Patrikar Electronics 12 (1), 183, 2022 | 1 | 2022 |
| Systems and methods for storing data in an integrated array and linked list based structure MD Barve, SA Puranik, M Nambiar, R Swapnil US Patent 11,263,203, 2022 | 1 | 2022 |
| Low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware D Shah, S Puranik, M Nambiar, MD Barve, I Shaikh, P Manavar, ... US Patent 11,736,594, 2023 | | 2023 |
| Re-assembly middleware in FPGA for processing TCP segments into application layer messages D Shah, S Puranik, M Nambiar, MD Barve, I Shaikh US Patent 11,611,638, 2023 | | 2023 |
| Acceleration of Trading System Back End with FPGAs Using High-Level Synthesis Flow S Puranik, M Barve, S Rodi, R Patrikar Electronics 12 (3), 520, 2023 | | 2023 |
| Acceleration of Trading System Back End with FPGAs Using High-Level Synthesis Flow. Electronics 2023, 12, 520 S Puranik, M Barve, S Rodi, R Patrikar Applications Enabled by FPGA-Based Technology, 19, 2023 | | 2023 |
| Multiple field programmable gate array (FPGA) based multi-legged order transaction processing system and method thereof MD Barve, S Puranik, R Swapnil, M Nambiar, D Shah US Patent 11,263,164, 2022 | | 2022 |
| Method and system for message based communication and failure recovery for FPGA middleware framework MK Nambiar, R Swapnil, S Puranik, MD Barve US Patent 11,212,218, 2021 | | 2021 |
| IRC Computation Optimisation M Barve, A Kalele, M Nambiar NVidia Global Technology Conference(GTC2015), 2015 | | 2015 |
| Incremental Risk Charge Calculation: A case study of performance optimization on many/multi core platforms A Kalele, M Nambiar, M Barve Computer Measurement Group,2014, 2014 | | 2014 |
| Design of AQM routers supporting TCP flows using optimal control approach M Barve, H Pillai International Conference on Emerging Research in Computing, Information …, 2014 | | 2014 |
| Application of Control Theory to Communication Network M Barve, H Pillai M.Tech Thesis, 2005 | | 2005 |
| Control theory applied for TCP/AQM Problem M Barve, H Pillai National Systems Conference,2014, 2004 | | 2004 |
