| Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations G Mariniello, RT Doria, M de Souza, MA Pavanello, RD Trevisoli 2012 8th International Caribbean Conference on Devices, Circuits and Systems …, 2012 | 19 | 2012 |
| Hot carrier degradation in nanowire transistors: physical mechanisms, width dependence and impact of self-heating A Laurent, X Garros, S Barraud, G Mariniello, G Reimbold, D Roy, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 18 | 2016 |
| Underestimation of measured self‐heating in nanowires by using gate resistance technique G Mariniello, M Cassé, G Reimbold, MA Pavanello Electronics Letters 52 (23), 1935-1937, 2016 | 9 | 2016 |
| A simulation study of self-heating effect on junctionless nanowire transistors G Mariniello, MA Pavanello 2014 29th Symposium on Microelectronics Technology and Devices (SBMicro), 1-4, 2014 | 7 | 2014 |
| Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K G Mariniello, S Barraud, M Vinet, M Cassé, O Faynot, J Calcade, ... Solid-State Electronics 194, 108337, 2022 | 5 | 2022 |
| Experimental analysis of self-heating effects using the pulsed iv method in junctionless nanowire transistors FE Bergamaschi, G Mariniello, S Barraud, MA Pavanello 2018 33rd Symposium on microelectronics technology and devices (SBMicro), 1-4, 2018 | 5 | 2018 |
| Analysis of charges densities in multiple-gates SOI nMOS junctionless G Mariniello, A Cerdeira, M Estrada, RT Doria, RD Trevisoli, M de Souza, ... 28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 1-4, 2013 | 5 | 2013 |
| Self-heating-based analysis of gate structures on junctionless nanowire transistors FE Bergamaschi, MA Pavanello, G Mariniello 2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro), 1-4, 2017 | 3 | 2017 |
| Electrical characterization of stacked SOI nanowires at low temperatures JC Rodrigues, G Mariniello, M Casse, S Barraud, M Vinet, O Faynot, ... Solid-State Electronics 191, 108260, 2022 | 2 | 2022 |
| Analog characteristics of n-type vertically stacked nanowires G Mariniello, CAB de Carvalho, BC Paz, S Barraud, M Vinet, O Faynot, ... Solid-State Electronics 185, 108127, 2021 | 2 | 2021 |
| Temperature influence on the electrical properties of vertically stacked nanowire MOSFETs JC Rodrigues, G Mariniello, M Cassé, S Barraud, M Vinet, O Faynot, ... 2021 35th Symposium on Microelectronics Technology and Devices (SBMicro), 1-4, 2021 | 2 | 2021 |
| Evaluation of analog characteristics of n-type vertically stacked nanowires G Mariniello, S Barraud, M Vinet, O Faynot, BC Paz, MA Pavanello 2020 Joint International EUROSOI Workshop and International Conference on …, 2020 | 2 | 2020 |
| Simulation comparison of self-heating effects in junctionless nanowire transistors and finFET devices G Mariniello, M Pavanello ECS Transactions 66 (1), 259, 2015 | 2 | 2015 |
| An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires M De Souza, JC Rodrigues, G Mariniello, M Cassé, S Barraud, M Vinet, ... 2022 IEEE 15th Workshop on Low Temperature Electronics (WOLTE), 1-4, 2022 | 1 | 2022 |
| Performance of Stacked SOI Nanowires in a Wide Temperature Range JC Rodrigues, G Mariniello, M Cassé, S Barraud, M Vinet, O Faynot, ... 2021 Joint International EUROSOI Workshop and International Conference on …, 2021 | | 2021 |
| Efeitos do autoaquecimento em transistores SOI-MOS tridimensionais nanométricos GM Silva Centro Universitário FEI, São Bernardo do Campo, 2016 | | 2016 |
| Intrinsic Gate Capacitances of n-type Junctionless Nanowire Transistors Using a Three-Dimensional Device Simulation and Experimental Measurements G Mariniello, RT Doria, RD Trevisoli, M de Souza, MA Pavanello ECS Transactions 49 (1), 231, 2012 | | 2012 |
| Estudo das capacitâncias de porta em transistores MOS sem junção GM Silva Centro Universitário da FEI, São Bernardo do Campo, 2012 | | 2012 |
