| A low area high speed FPGA implementation of AES architecture for cryptography application TM Kumar, KS Reddy, S Rinaldi, BD Parameshachari, K Arunachalam Electronics 10 (16), 2023, 2021 | 79 | 2021 |
| FPGA implementation of an optimized key expansion module of AES algorithm for secure transmission of personal ECG signals PK TM Kumar Design Automation for Embedded Systems An International Journal, 2017 | 24* | 2017 |
| An optimized s-box circuit for high speed AES design with enhanced PPRM architecture to secure mammographic images T Manojkumar, P Karthigaikumar, V Ramachandran Journal of medical systems 43, 1-8, 2019 | 15 | 2019 |
| A novel method of improvement in advanced encryption standard algorithm with dynamic shift rows, sub byte and mixcolumn operations for the secure communication KP Manoj Kumar T International Journal of Information Technology 12 (1), 825-830, 2020 | 12 | 2020 |
| Implementation of a High-Speed and High-Throughput Advanced Encryption Standard TM Kumar, P Karthigaikumar INTELLIGENT AUTOMATION AND SOFT COMPUTING 31 (2), 1025-1036, 2021 | 7* | 2021 |
| Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data TM Kumar, KR Balmuri, A Marchewka, P Bidare Divakarachari, S Konda Sensors 21 (24), 8347, 2021 | 3 | 2021 |
| An Efficient Performance Analysis of Different Adder Topologies TM Kumar, S Navaneethan, AC Murugesapandian | 1 | 2015 |
| AES Algorithm for the Next Generation of 5G Network Encryption Standards T Manojkumar, K Tamilarasi, S Mahalakshmi, P Vinayagam, ... 2023 International Conference on Advances in Computing, Communication and …, 2023 | | 2023 |
| An Effective Software Based Method to Analyze SCA Countermeasures for Advanced Encryption Standard T Manoj Kumar, P Karthigaikumar Wireless Personal Communications 123 (3), 2937-2958, 2022 | | 2022 |
| Smart System for Monitoring Air Pollutants from Industries DPK Manoj Kumar. T IJSART 2 (2), 192-195, 2016 | | 2016 |
| An Intelligent Traffic Monitoring System TM Kumar International Journal of Advanced Research in Computer Science and Software …, 2015 | | 2015 |
| COMPARISON ON VARIOUS ADDERS AND MULTIPLIERS IN DIFFERENT FPGA’S ARCHITECTURES AND ASIC AND THEIR PERFORMANCE STUDY M Kumar T International Journal of Applied Engineering Research 10 (20), 19393-19398, 2015 | | 2015 |
| “An Efficient Performance Analysis of Different Adder Topologies” M T International Journal of Computer Science and Mobile Computing 4 (1), 284-290, 2015 | | 2015 |
| Analysis of DC Characteristics and short Channel effects in Junctionless FINFET CJ Manoj Kumar.T International Conference on Knowledge Collaboration in Engineering 2014, 2014 | | 2014 |
| Past,Present and Future of Nano CMOS Technologies IEEE, 2013 | | 2013 |
| A Bist Scheme for testing the SRAM based FPGA's Faults M Kumar T International Conference on Recent Advancements in Engineering and …, 2013 | | 2013 |
| A Bist Scheme for testing the SRAM based FPGA M Kumar T National Conference on Advanced computational Intellegience Systems 1, 501-506, 2013 | | 2013 |
| A Bist scheme for testing the SRAM based FPGA's Faults M Kumar T CAREER'13 1, 2013 | | 2013 |
| A fast Low power Modulo 2n+1 multiplier M Kumar T National level conference on Innovations in Engineering and Technology 1 …, 2012 | | 2012 |
| Transmission Lines and WaveGuides NB Manoj Kumar.T Anuradha Publications, 0 | | |
