Chunyue Liu
Cited by
Cited by
Quantitative studies of impact of 3D IC design on repeater usage
J Cong, C Liu, G Luo
Proceedings of International VLSI/ULSI Multilevel Interconnection Conference …, 2008
Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design
YT Chen, J Cong, H Huang, B Liu, C Liu, M Potkonjak, G Reinman
Power reduction of CMP communication networks via RF-interconnects
MCF Chang, J Cong, A Kaplan, C Liu, M Naik, J Premkumar, G Reinman, ...
2008 41st IEEE/ACM International Symposium on Microarchitecture, 376-387, 2008
An energy-efficient adaptive hybrid cache
J Cong, K Gururaj, H Huang, C Liu, G Reinman, Y Zou
IEEE/ACM International Symposium on Low Power Electronics and Design, 67-72, 2011
Static and dynamic co-optimizations for blocks mapping in hybrid caches
YT Chen, J Cong, H Huang, C Liu, R Prabhakar, G Reinman
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Accelerator-rich CMPs: From concept to real hardware
YT Chen, J Cong, MA Ghodrat, M Huang, C Liu, B Xiao, Y Zou
2013 IEEE 31st International Conference on Computer Design (ICCD), 169-176, 2013
A reuse-aware prefetching scheme for scratchpad memory
J Cong, H Huang, C Liu, Y Zou
Proceedings of the 48th Design Automation Conference, 960-965, 2011
Evaluation of static analysis techniques for fixed-point precision optimization
J Cong, K Gururaj, B Liu, C Liu, Z Zhang, S Zhou, Y Zou
2009 17th IEEE Symposium on Field Programmable Custom Computing Machines …, 2009
BiN: A buffer-in-NUCA Scheme for Accelerator-rich CMPs
J Cong, MA Ghodrat, M Gill, C Liu, G Reinman
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Aces: Application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip
J Cong, C Liu, G Reinman
Design Automation Conference (DAC), 2010 47th ACM/IEEE, 443-448, 2010
AXR-CMP: Architecture Support in Accelerator-Rich CMPs
J Cong, MA Ghodrat, M Gill, C Liu, G Reinman, Y Zou
Proc. 2nd Workshop on SoC Architecture, Accelerators and Workloads (SAW-2 …, 2011
Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects
C Xiao, MC Frank Chang, J Cong, M Gill, Z Huang, C Liu, G Reinman, ...
ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-27, 2013
On-chip radio frequency (RF) interconnects for network-on-chip designs
MCF Chang, C Jason, A Kaplan, M Naik, G Reinman, E Socher, SW Tam, ...
US Patent 8,270,316, 2012
An optimized linear skewing interleave scheme for on-chip multi-access memory systems
C Liu, X Yan, X Qin
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 8-13, 2007
An efficient 2-D stream memory system for video processing
C Liu, H Ge, X Yan
Journal of Southern Yangtze University - Natural Science 7 (001), 6-10, 2008
Architecture Support for Customizable Domain-Specific Computing
C Liu
University of California, Los Angeles, 2012
Revisiting bitwidth optimizations
J Cong, K Gururaj, B Liu, C Liu, Y Zou, Z Zhang, S Zhou
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2009
Multimedia memory architecture with 2-D addressing and data permutation embedding
X Qin, C Liu
Computer Engineering and Applications 44 (7), 2008
Explicit data organization SIMD instruction set architecture for media processors.
C Liu, X Qin, X Yan
Parallel and Distributed Computing and Networks, 212-217, 2007
Architectural Optimization of Data Storage and Organization for SIMD Media Processors
C Liu
Zhejiang University, 2007
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